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74LV4020N

Description
Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT
Categorylogic    logic   
File Size100KB,21 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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74LV4020N Overview

Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT

74LV4020N Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknown
Other featuresOUTPUTS FROM 12 STAGES AVAILABLE
Counting directionUP
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDIP-T16
JESD-609 codee4
length19.025 mm
Load capacitance (CL)50 pF
Load/preset inputNO
Logic integrated circuit typeBINARY COUNTER
Maximum Frequency@Nom-Sup20000000 Hz
MaximumI(ol)0.006 A
Operating modeASYNCHRONOUS
Number of digits14
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT APPLICABLE
power supply3.3 V
propagation delay (tpd)54 ns
Certification statusNot Qualified
Maximum seat height4.2 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT APPLICABLE
Trigger typeNEGATIVE EDGE
width7.62 mm
minfmax36 MHz
Base Number Matches1
74LV4020
14-stage binary ripple counter
Rev. 01 — 29 November 2005
Product data sheet
1. General description
The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible
with the 74HC4020 and 74HCT4020.
The 74LV4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and 12 fully buffered parallel outputs (Q0, and
Q3 to Q13).
The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all
counter stages and forces all outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
2. Features
s
Optimized for low-voltage applications: 1.0 V to 5.5 V
s
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
s
Typical LOW-level output voltage (peak) or output ground bounce: V
OL(p)
< 0.8 V at
V
CC
= 3.3 V and T
amb
= 25
°C
s
Typical HIGH-level output voltage (valley) or output V
OH
undershoot: V
OH(v)
> 2 V at
V
CC
= 3.3 V and T
amb
= 25
°C
s
ESD protection:
x
HBM EIA/JESD22-A114-C exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C.
3. Applications
s
Frequency dividing circuits
s
Time delay circuits
s
Control counters

74LV4020N Related Products

74LV4020N 74LV4020DB-T 74LV4020D 74LV4020D-T 74LV4020PW 74LV4020DB
Description Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT Counter ICs 14ST BIN RIP COUNTER Counter ICs 3.3V 14-STAGE BIN RIPPLE COUNT
Maker NXP NXP NXP NXP NXP NXP
Parts packaging code DIP SSOP SOIC SOIC TSSOP SSOP
package instruction DIP, DIP16,.3 SSOP, SOP, SOP16,.25 SOP, TSSOP, TSSOP16,.25 SSOP, SSOP16,.3
Contacts 16 16 16 16 16 16
Reach Compliance Code unknown unknown unknown unknown compliant compliant
Base Number Matches 1 1 1 1 1 1
Is it Rohs certified? conform to - conform to - conform to conform to
Other features OUTPUTS FROM 12 STAGES AVAILABLE OUTPUTS FROM 12 STAGES AVAILABLE OUTPUTS FROM 12 STAGES AVAILABLE OUTPUTS FROM 12 STAGES AVAILABLE - OUTPUTS FROM 12 STAGES AVAILABLE
Counting direction UP UP UP UP - UP
series LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H - LV/LV-A/LVX/H
JESD-30 code R-PDIP-T16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 - R-PDSO-G16
JESD-609 code e4 e4 e4 - - e4
length 19.025 mm 6.2 mm 9.9 mm 9.9 mm - 6.2 mm
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF - 50 pF
Load/preset input NO YES NO YES - NO
Logic integrated circuit type BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER - BINARY COUNTER
Operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS - ASYNCHRONOUS
Number of digits 14 14 14 14 - 14
Number of functions 1 1 1 1 - 1
Number of terminals 16 16 16 16 - 16
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C - 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C - -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code DIP SSOP SOP SOP - SSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR - RECTANGULAR
Package form IN-LINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE - SMALL OUTLINE, SHRINK PITCH
propagation delay (tpd) 54 ns 54 ns 54 ns 54 ns - 54 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified - Not Qualified
Maximum seat height 4.2 mm 2 mm 1.75 mm 1.75 mm - 2 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V - 5.5 V
Minimum supply voltage (Vsup) 1 V 1 V 1 V 1 V - 1 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V - 3.3 V
surface mount NO YES YES YES - YES
technology CMOS CMOS CMOS CMOS - CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE - AUTOMOTIVE
Terminal surface NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD Nickel/Palladium/Gold (Ni/Pd/Au) - - Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form THROUGH-HOLE GULL WING GULL WING GULL WING - GULL WING
Terminal pitch 2.54 mm 0.65 mm 1.27 mm 1.27 mm - 0.65 mm
Terminal location DUAL DUAL DUAL DUAL - DUAL
Trigger type NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE - NEGATIVE EDGE
width 7.62 mm 5.3 mm 3.9 mm 3.9 mm - 5.3 mm
minfmax 36 MHz 36 MHz 36 MHz 36 MHz - 36 MHz

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