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TC7MET138AFK

Description
3-to-8 Line Decoder
Categorylogic    logic   
File Size181KB,6 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
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TC7MET138AFK Overview

3-to-8 Line Decoder

TC7MET138AFK Parametric

Parameter NameAttribute value
MakerToshiba Semiconductor
Parts packaging codeSOIC
package instructionSOP, TSSOP16,.16,20
Contacts16
Reach Compliance Codeunknow
Other features3 ENABLE INPUTS
seriesAHCT/VHCT
JESD-30 codeR-PDSO-G16
JESD-609 codee0
Load capacitance (CL)50 pF
Logic integrated circuit typeOTHER DECODER/DRIVER
MaximumI(ol)0.008 A
Number of functions1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityINVERTED
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeTSSOP16,.16,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Prop。Delay @ Nom-Su13 ns
propagation delay (tpd)13 ns
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
TC7MET138AFK
TOSHIBA CMOS Didital Integrated Circuit
Silicon Monolithic
TC7MET138AFK
3-to-8 Line Decoder
The TC7MET138AFK is an advanced high speed CMOS 3-to-8
line decoder fabricated with silicon gate C
2
MOS technology. It
achieves the high speed operation similar to equivalent bipolar
schottky TTL while maintaining the CMOS low power
dissipation.
When the device is enabled, 3 binary select inputs (A, B and C)
determine which one of the outputs (Y0 - Y7) will go low.
When enable input G1 is held low or either G2A or G2B is held
high, decoding function is inhibited and all outputs go high. G1,
G2A, and G2B inputs are provided to ease cascade connection
and for use as an address decoder for memory systems.
The input voltage are compatible with TTL output voltage.
Weight: 0.02 g (typ.)
This device may be used as a level converter for interfacing 3.3
V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output
(Note)
pins
without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and
input/output voltages such as battery back up, hot board insertion, etc.
Note: V
CC
=
0 V
Features
High speed: t
pd
= 7.6 ns (typ.) (V
CC
= 5 V)
Low power dissipation: I
CC
= 4
μA
(max) (Ta = 25°C)
Compatible with TTL outputs: V
IL
= 0.8 V (max)
V
IH
= 2.0 V (min)
Power down protection is provided on all inputs and outputs.
Balanced propagation delays: t
pLH
t
pHL
Pin and function compatible with the 74 series (74AC/HC/ALS/LS etc.) 138 type.
1
2007-10-19

TC7MET138AFK Related Products

TC7MET138AFK TC7MET138AFK_07
Description 3-to-8 Line Decoder 3-to-8 Line Decoder

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