54F 74F646
74F646B
54F 74F648 Octal Transceiver Register with TRI-STATE Outputs
December 1994
54F 74F646
74F646B
54F 74F648
Octal Transceiver Register with TRI-STATE Outputs
General Description
These devices consist of bus transceiver circuits with TRI-
STATE D-type flip-flops and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level Control G and direction pins are provid-
ed to control the transceiver function In the transceiver
mode data present at the high impedance port may be
stored in either the A or the B register or in both The select
controls can multiplex stored and real-time (transparent
mode) data The direction control determines which bus will
receive data when the enable control G is Active LOW In
the isolation mode (control G HIGH) A data may be stored
in the B register and or B data may be stored in the A regis-
ter
Features
Y
Y
Y
Y
Y
Y
Y
Y
Independent registers for A and B buses
Multiplexed real-time and stored data
’F648 has inverting data paths
’F646 ’F646B have non-inverting data paths
’F646B is a faster version of the ’F646
TRI-STATE outputs
300 mil slim DIP
Guaranteed 4000V minimum ESD protection
Commercial
74F646SPC
Military
Package
Number
N24C
Package Description
24-Lead (0 300 Wide) Molded Dual-In-Line
24-Lead (0 300 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Molded Small Outline JEDEC
24-Lead Molded Shrink Small Outline EIAJ Type II
24-Lead Cerpack
28-Lead Ceramic Leadless Chip Carrier Type C
24-Lead (0 300 Wide) Molded Dual-In-Line
24-Lead (0 300 Wide) Molded Small Outline JEDEC
24-Lead (0 300 Wide) Molded Dual-In-Line
24-Lead (0 300 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Molded Small Outline JEDEC
24-Lead Cerpack
24-Lead Ceramic Leadless Chip Carrier Type C
54F646DM (Note 2)
74F646SC (Note 1)
74F646MSA (Note 1)
54F646FM (Note 2)
54F646LM (Note 2)
74F646BSPC
74F646BSC (Note 1)
74F648SPC
54F648SDM (Note 2)
74F648SC (Note 1)
54F648FM (Note 2)
54F648LM (Note 2)
Note 1
Devices also available in 13 reel Use suffix
e
SCX
J24F
M24B
MSA24
W24C
E28A
N24C
M24B
N24C
J24F
M24B
W24C
E28A
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
’F646 ’F646B
’F648
TL F 9580 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9580
TL F 9580 – 7
RRD-B30M75 Printed in U S A
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
Input I
IH
I
IL
Output I
OH
I
OL
Data Register A Inputs
TRI-STATE Outputs
B
0
–B
7
Data Register B Inputs
TRI-STATE Outputs
CPAB CPBA Clock Pulse Inputs
SAB SBA
Select Inputs
G
Output Enable Input
DIR
Direction Control Input
A
0
–A
7
3 5 1 083
70
mA
b
650
mA
600 106 6 (80)
b
12 mA 64 mA (48 mA)
3 5 1 083
70
mA
b
650
mA
b
12 mA 64 mA (48 mA)
600 106 6 (80)
10 10
20
mA
b
0 6 mA
10 10
20
mA
b
0 6 mA
10 10
20
mA
b
0 6 mA
10 10
20
mA
b
0 6 mA
Function Table
Inputs
G
H
H
H
L
L
L
L
L
L
L
L
DIR
X
X
X
H
H
H
H
L
L
L
L
CPAB
H or L
L
X
X
L
H or L
L
X
X
X
X
CPBA
H or L
X
L
X
X
X
X
X
L
H or L
L
SAB
X
X
X
L
L
H
H
X
X
X
X
SBA
X
X
X
X
X
X
X
L
L
H
H
Data I O
A
0
–A
7
Input
B
0
–B
7
Input
Function
Isolation
Clock A
n
Data into A Register
Clock B
n
Data into B Register
A
n
to B
n
Real Time (Transparent Mode)
Clock A
n
Data into A Register
A Register to B
n
(Stored Mode)
Clock A
n
Data into A Register and Output to B
n
B
n
to A
n
Real Time (Transparent Mode)
Clock B
n
Data into B Register
B Register to A
n
(Stored Mode)
Clock B
n
Data into B Register and Output to A
n
Input
Output
Output
Input
The data output functions may be enabled or disabled by various signals at the G and DIR Inputs Data input functions are always enabled i e data at the bus
pins will be stored on every LOW-to-HIGH transition of the clock inputs
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Irrelevant
L
e
LOW-to-HIGH Transition
3
DSP and ARM Processors
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