54RHSC109CD datasheet, PDF - EEWORLD Datasheet

54RHSC109CD: DescriptionJ-Kbar Flip-Flop, HSC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16; Categorylogic; File Size2MB，84 Pages; ManufacturerDynex; Websitehttp://www.dynexsemi.com/

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54RHSC109CD Overview

J-Kbar Flip-Flop, HSC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16

Parameter Name	Attribute value
Maker	Dynex
package instruction	,
Reach Compliance Code	unknown
Is Samacsys	N
Other features	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHNOLOGY
series	HSC
JESD-30 code	R-CDIP-T16
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-KBAR FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
Package shape	RECTANGULAR
Package form	IN-LINE
propagation delay (tpd)	25 ns
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal location	DUAL
Trigger type	POSITIVE EDGE
Base Number Matches	1

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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