D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
MC34166, MC33166
3.0 A, Step−Up/Down/
Inverting Switching
Regulators
The MC34166, MC33166 series are high performance fixed
frequency power switching regulators that contain the primary
functions required for dc−to−dc converters. This series was specifically
designed to be incorporated in step−down and voltage−inverting
configurations with a minimum number of external components and
can also be used cost effectively in step−up applications.
These devices consist of an internal temperature compensated
reference, fixed frequency oscillator with on−chip timing components,
latching pulse width modulator for single pulse metering, high gain
error amplifier, and a high current output switch.
Protective features consist of cycle−by−cycle current limiting,
undervoltage lockout, and thermal shutdown. Also included is a low
power standby mode that reduces power supply current to 36
mA.
Features
http://onsemi.com
x
A
WL
Y
WW
G
= 3 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
MARKING
DIAGRAMS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Output Switch Current in Excess of 3.0 A
Fixed Frequency Oscillator (72 kHz) with On−Chip Timing
Provides 5.05 V Output without External Resistor Divider
Precision 2% Reference
0% to 95% Output Duty Cycle
Cycle−by−Cycle Current Limiting
Undervoltage Lockout with Hysteresis
Internal Thermal Shutdown
Operation from 7.5 V to 40 V
Standby Mode Reduces Power Supply Current to 36
mA
Economical 5−Lead TO−220 Package with Two Optional Leadforms
Also Available in Surface Mount D
2
PAK Package
Moisture Sensitivity Level (MSL) Equals 1
Pb−Free Packages are Available
V
in
I
LIMIT
Oscillator
4
TO−220
TH SUFFIX
CASE 314A
1
5
MC
3x166T
AWLYWWG
1
5
TO−220
TV SUFFIX
CASE 314B
MC
3x166T
AWLYWWG
Heatsink surface connected to Pin 3
TO−220
T SUFFIX
CASE 314D
1
MC
3x166T
AWLYWWG
S
Q
R
2
5
Pin
1.
2.
3.
4.
5.
Voltage Feedback Input
Switch Output
Ground
Input Voltage/V
CC
Compensation/Standby
D
2
PAK
D2T SUFFIX
CASE 936A
5
Heatsink surface (shown as
terminal 6 in case outline
drawing) is connected to Pin 3
1
5
MC
3x166T
AWLYWWG
PWM
UVLO
Thermal
Reference
EA
1
V
O
5.05 V/
3.0 A
3
5
This device contains 143 active transistors.
L
1
Figure 1. Simplified Block Diagram
(Step Down Application)
©
Semiconductor Components Industries, LLC, 2005
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1
October, 2005 − Rev. 7
Publication Order Number:
MC34166/D
MC34166, MC33166
ORDERING INFORMATION
Device
MC33166D2T
MC33166D2TG
MC33166D2TR4
MC33166D2TR4G
MC33166T
MC33166TG
MC33166TH
MC33166THG
MC33166TV
MC33166TVG
MC34166D2T
MC34166D2TG
MC34166D2TR4
MC34166D2TR4G
MC34166T
MC34166TG
MC34166TH
MC34166THG
MC34166TV
MC34166TVG
T
A
= 0° to +70°C
T
A
= −40° to +85°C
Operating
Temperature Range
Package
D
2
PAK − Surface Mount
D
2
PAK − Surface Mount
(Pb−Free)
D
2
PAK − Surface Mount
D
2
PAK − Surface Mount
(Pb−Free)
TO−220 − Straight Lead
TO−220 − Straight Lead
(Pb−Free)
TO−220 − Horizontal Mount
TO−220 − Horizontal Mount
(Pb−Free)
TO−220 − Vertical Mount
TO−220 − Vertical Mount
(Pb−Free)
D
2
PAK − Surface Mount
D
2
PAK − Surface Mount
(Pb−Free)
D
2
PAK − Surface Mount
D
2
PAK − Surface Mount
(Pb−Free)
TO−220 − Straight Lead
TO−220 − Straight Lead
(Pb−Free)
TO−220 − Horizontal Mount
TO−220 − Horizontal Mount
(Pb−Free)
TO−220 − Vertical Mount
TO−220 − Vertical Mount
(Pb−Free)
50 Units/Rail
800 / Tape & Reel
800 / Tape & Reel
50 Units/Rail
Shipping
†
50 Units/Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
Rating
Power Supply Input Voltage
Switch Output Voltage Range
Voltage Feedback and Compensation Input Voltage Range
Power Dissipation
Case 314A, 314B and 314D (T
A
= +25°C)
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
Case 936A (D
2
PAK) (T
A
= +25°C)
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
Operating Junction Temperature
Operating Ambient Temperature (Note 2)
MC34166
MC33166
Symbol
V
CC
V
O(switch)
V
FB,
V
Comp
P
D
q
JA
q
JC
P
D
q
JA
q
JC
T
J
T
A
Value
40
−1.5 to + V
in
−1.0 to + 7.0
Internally Limited
65
5.0
Internally Limited
70
5.0
+150
0 to + 70
− 40 to + 85
Unit
V
V
V
W
°C/W
°C/W
W
°C/W
°C/W
°C
°C
Storage Temperature Range
T
stg
− 65 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL−STD−883, Method 3015.
Machine Model Method 200 V.
2. T
low
= 0°C for MC34166
T
high
= + 70°C for MC34166
= − 40°C for MC33166
= + 85°C for MC33166
http://onsemi.com
2
MC34166, MC33166
ELECTRICAL CHARACTERISTICS
(V
CC
= 12 V, for typical values T
A
= +25°C, for min/max values T
A
is the operating ambient
temperature range that applies [Notes 3, 4], unless otherwise noted.)
Characteristic
OSCILLATOR
Frequency (V
CC
= 7.5 V to 40 V)
ERROR AMPLIFIER
Voltage Feedback Input Threshold
T
A
= +25°C
T
A
= T
low
to T
high
V
FB(th)
Reg
line
I
IB
PSRR
V
OH
V
OL
4.95
4.85
−
−
60
4.2
−
5.05
−
0.03
0.15
80
4.9
1.6
5.15
5.2
0.078
1.0
−
−
1.9
V
%/V
mA
dB
V
T
A
= +25°C
T
A
= T
low
to T
high
f
OSC
65
62
72
−
79
81
kHz
Symbol
Min
Typ
Max
Unit
Line Regulation (V
CC
= 7.5 V to 40 V, T
A
= +25°C)
Input Bias Current (V
FB
= V
FB(th)
+ 0.15 V)
Power Supply Rejection Ratio (V
CC
= 10 V to 20 V, f = 120 Hz)
Output Voltage Swing
High State (I
Source
= 75
mA,
V
FB
= 4.5 V)
Low State (I
Sink
= 0.4 mA, V
FB
= 5.5 V)
PWM COMPARATOR
Duty Cycle
Maximum (V
FB
= 0 V)
Minimum (V
Comp
= 1.9 V)
SWITCH OUTPUT
Output Voltage Source Saturation (V
CC
= 7.5 V, I
Source
= 3.0 A)
Off−State Leakage (V
CC
= 40 V, Pin 2 = GND)
Current Limit Threshold
Switching Times (V
CC
= 40 V, I
pk
= 3.0 A, L = 375
mH,
T
A
= +25°C)
Output Voltage Rise Time
Output Voltage Fall Time
UNDERVOLTAGE LOCKOUT
Startup Threshold (V
CC
Increasing, T
A
= +25°C)
Hysteresis (V
CC
Decreasing, T
A
= +25°C)
TOTAL DEVICE
Power Supply Current (T
A
= +25°C )
Standby (V
CC
= 12 V, V
Comp
< 0.15 V)
Operating (V
CC
= 40 V, Pin 1 = GND for maximum duty cycle)
%
DC
(max)
DC
(min)
V
sat
I
sw(off)
I
pk(switch)
t
r
t
f
V
th(UVLO)
V
H(UVLO)
I
CC
−
−
36
31
100
55
92
0
95
0
100
0
−
−
3.3
−
−
(V
CC
−1.5)
0
4.3
100
50
(V
CC
−1.8)
100
6.0
200
100
V
mA
A
ns
5.5
0.6
5.9
0.9
6.3
1.2
V
V
mA
mA
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
4. T
low
= 0°C for MC34166
T
high
= + 70°C for MC34166
= − 40°C for MC33166
= + 85°C for MC33166
http://onsemi.com
3
MC34166, MC33166
V FB(th), VOLTAGE FEEDBACK INPUT THRESHOLD (V)
5.25
V
CC
= 12 V
5.17
5.09
5.01
V
FB(th)
Min = 4.95 V
4.93
4.85
− 55
V
FB(th)
Max = 5.15 V
100
IIB, INPUT BIAS CURRENT (nA)
80
60
40
20
0
− 55
V
CC
= 12 V
V
FB
= V
FB(th)
V
FB(th)
Typ = 5.05 V
− 25
0
25
50
75
T
A
, AMBIENT TEMPERATURE (°C)
100
125
− 25
0
25
50
75
T
A
, AMBIENT TEMPERATURE (°C)
100
125
Figure 2. Voltage Feedback Input Threshold
versus Temperature
Figure 3. Voltage Feedback Input Bias
Current versus Temperature
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
80
Gain
60
40
30
60
90
φ
, EXCESS PHASE (DEGREES)
V
CC
= 12 V
V
Comp
= 3.25 V
R
L
= 100 k
T
A
= +25°C
0
Vsat , OUTPUT SATURATION VOLTAGE (V)
100
2.0
1.6
1.2
0.8
0.4
0
Phase
20
0
120
150
180
10 M
V
CC
= 12 V
V
FB
= 5.5 V
T
A
= +25°C
− 20
10
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
1.0 M
0
0.4
0.8
1.2
1.6
I
Sink
, OUTPUT SINK CURRENT (mA)
2.0
Figure 4. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 5. Error Amp Output Saturation
versus Sink Current
Δ
f OSC, OSCILLATOR FREQUENCY CHANGE (%)
DC, SWITCH OUTPUT DUTY CYCLE (%)
4.0
V
CC
= 12 V
0
100
80
60
40
20
0
1.5
V
CC
= 12 V
T
A
= +25°C
− 4.0
− 8.0
− 12
− 55
− 25
0
25
50
75
100
T
A
, AMBIENT TEMPERATURE (°C)
125
2.0
2.5
3.0
3.5
4.0
V
Comp
, COMPENSATION VOLTAGE (V)
4.5
Figure 6. Oscillator Frequency Change
versus Temperature
Figure 7. Switch Output Duty Cycle
versus Compensation Voltage
http://onsemi.com
4
京公网安备 11010802033920号
EEWORLD
