NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5775E
Rev. 1, 05/2018
MPC5775E/MPC5775B
Microcontroller Data Sheet
Features
• This document provides electrical specifications, pin
assignments, and package diagram information for the
MPC5775E series of microcontroller units (MCUs).
MPC5775E
• For functional characteristics and the programming
model, see the MPC5775E Reference Manual.
NXP reserves the right to change the proudction detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1 Introduction...............................................................................3
1.1
1.2
Features summary..........................................................3
Block diagram..................................................................4
3.11.1
3.11.2
3.11.3
3.11.4
Power management electrical characteristics. .37
Power management integration........................39
Device voltage monitoring................................41
Power sequencing requirements......................43
2 Pinouts......................................................................................5
2.1
416-ball MAPBGA pin assignments................................5
3.12 Flash memory specifications...........................................44
3.12.1
Flash memory program and erase
specifications....................................................45
3.12.2
Flash memory Array Integrity and Margin
Read specifications..........................................45
3.12.3
3.12.4
3.12.5
3.12.6
Flash memory module life specifications..........46
Data retention vs program/erase cycles...........47
Flash memory AC timing specifications............47
Flash memory read wait-state and address-
pipeline control settings....................................48
3.13 AC timing.........................................................................49
3.13.1
3.13.2
3.13.3
3.13.4
3.13.5
3.13.6
3.13.7
3.13.8
3.13.9
Generic timing diagrams...................................49
Reset and configuration pin timing...................50
IEEE 1149.1 interface timing............................51
Nexus timing.....................................................54
External interrupt timing (IRQ/NMI pin)............56
eTPU timing......................................................57
eMIOS timing....................................................57
DSPI timing with CMOS and LVDS pads.........58
FEC timing........................................................70
3 Electrical characteristics............................................................6
3.1
3.2
3.3
3.4
3.5
3.6
Absolute maximum ratings..............................................6
Electromagnetic interference (EMI) characteristics.........8
Electrostatic discharge (ESD) characteristics.................8
Operating conditions.......................................................8
DC electrical specifications.............................................11
I/O pad specifications......................................................12
3.6.1
3.6.2
3.6.3
3.7
Input pad specifications....................................12
Output pad specifications.................................14
I/O pad current specifications...........................17
Oscillator and PLL electrical specifications.....................17
3.7.1
3.7.2
PLL electrical specifications.............................18
Oscillator electrical specifications.....................19
3.8
Analog-to-Digital Converter (ADC) electrical
specifications...................................................................21
3.8.1
Enhanced Queued Analog-to-Digital
Converter (eQADC)..........................................21
3.8.2
Sigma-Delta ADC (SDADC).............................23
3.9
Temperature Sensor.......................................................31
3.10 LVDS pad electrical characteristics.................................32
3.10.1
3.10.2
MSC/DSPI LVDS interface timing diagrams.....32
MSC/DSPI LVDS interface electrical
characteristics...................................................34
3.11 Power management: PMC, POR/LVD, power
sequencing......................................................................36
4 Package information.................................................................75
4.1
Thermal characteristics...................................................75
4.1.1
General notes for thermal characteristics.........76
5 Ordering information.................................................................79
6 Document revision history.........................................................79
MPC5775E/MPC5775B Microcontroller Data Sheet Data Sheet, Rev. 1, 05/2018.
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NXP Semiconductors
Introduction
1 Introduction
1.1 Features summary
On-chip modules available within the family include the following features:
• Three dual issue, 32-bit CPU core complexes (e200z7), two of which run in lockstep
• Power Architecture embedded specification compliance
• Instruction set enhancement allowing variable length encoding (VLE), optional
encoding of mixed 16-bit and 32-bit instructions, for code size footprint
reduction
• On the two computational cores: Signal processing extension (SPE1.1)
instruction support for digital signal processing (DSP)
• Single-precision floating point operations
• On the two computational cores: 16 KB I-Cache and 16 KB D-Cache
• Hardware cache coherency between cores
• 16 hardware semaphores
• 3-channel CRC module
• 4 MB on-chip flash memory
• Supports read during program and erase operations, and multiple blocks
allowing EEPROM emulation
• 512 KB on-chip general-purpose SRAM including 64 KB standby RAM
• Two multichannel direct memory access controllers (eDMA)
• 64 channels per eDMA
• Dual core Interrupt Controller (INTC)
• Dual phase-locked loops (PLLs) with stable clock domain for peripherals and
frequency modulation (FM) domain for computational shell
• Crossbar Switch architecture for concurrent access to peripherals, flash memory, or
RAM from multiple bus masters with End-To-End ECC
• System Integration Unit (SIU)
• Error Injection Module (EIM) and Error Reporting Module (ERM)
• Four protected port output (PPO) pins
• Boot Assist Module (BAM) supports serial bootload via CAN or SCI
• Up to three second-generation Enhanced Time Processor Units (eTPUs)
• 32 channels per eTPU
• Total of 36 KB code RAM
• Total of 9 KB parameter RAM
MPC5775E/MPC5775B Microcontroller Data Sheet Data Sheet, Rev. 1, 05/2018.
NXP Semiconductors
3
Introduction
• Enhanced Modular Input/Output System (eMIOS) supporting 32 unified channels
with each channel capable of single action, double action, pulse width modulation
(PWM) and modulus counter operation
• Up to two Enhanced Queued Analog-to-Digital Converter (eQADC) modules with:
• Two separate analog converters per eQADC module
• Support for a total of 70 analog input pins, expandable to 182 inputs with off-
chip multiplexers
• Up to four independent 16-bit Sigma-Delta ADCs (SDADCs)
• Ethernet (FEC)
• Two SENT Receiver (SRX) modules supporting 12 channels
• Five Deserial Serial Peripheral Interface (DSPI) modules
• Five Enhanced Serial Communication Interface (eSCI) modules
• Four Controller Area Network (FlexCAN) modules
• Two M_CAN modules that support FD
• Fault Collection and Control Unit (FCCU)
• Clock Monitor Units (CMUs)
• Tamper Detection Module (TDM)
• Cryptographic Services Engine (CSE)
• Complies with
Secure Hardware Extension (SHE) Functional Specification
Version 1.1
security functions
• Includes software selectable enhancement to key usage flag for MAC
verification and increase in number of memory slots for security keys
• PASS module to support security features
• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some
support for 2010 standard
• Device and board test support per Joint Test Action Group (JTAG) IEEE 1149.1 and
1149.7
• On-chip voltage regulator controller (VRC) that derives the core logic supply voltage
from the high-voltage supply
• On-chip voltage regulator for flash memory
• Self Test capability
1.2 Block diagram
The following figure shows a top-level block diagram of the MPC5777E. The purpose of
the block diagram is to show the general interconnection of functional modules through
the crossbar switch.
MPC5775E/MPC5775B Microcontroller Data Sheet Data Sheet, Rev. 1, 05/2018.
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NXP Semiconductors
Pinouts
COMPUTATIONAL SHELL
e200z7 checker
core complex
e200z7
(dual issue)
FPU
VLE
16K I-Cache
16K D-Cache
MMU
SWT
STM
INTC
e200z7
(dual issue)
FPU
VLE
16K I-Cache
16K D-Cache
MMU
64ch eDMA
64ch eDMA
Ethernet
SWT
STM
INTC
DEBUG
JTAG
Nexus 3+
MMU
DTS
FLEXCAN_A-B
MCAN_0-1
DSPI_A-C
eSCI_A-C
ETPU_C
w/RAM
eMIOS_0
eQADC_A
& Temp Sensors
SDADC_1/3
SRX_0
Dual PLL/
OSC/IRC
Crossbar Switch with ECC
MPU
Safety
Monitor
CRC
PCM/ERM
Bridge B
Flash Control
SRAM
Control
Security
Tamper
Detection
Flash w/ EEPROM
SRAM
CSE
Bridge A
FlexCAN_C-D
SDADC_2/4
SIU/SIU_B
ETPU_A/B
(w/RAM)
eQADC_B
DSPI_D-E
PMU/PMC
eSCI_D-F
CMU_0-8
eMIOS_1
PIT-RTI
2 Pinouts
2.1 416-ball MAPBGA pin assignments
Figure 2
shows the 416-ball MAPBGA pin assignments.
MPC5775E/MPC5775B Microcontroller Data Sheet Data Sheet, Rev. 1, 05/2018.
NXP Semiconductors
5
SRX_1
FCCU
Figure 1. MPC5775E block diagram
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