IP4791CZ12
HDMI ESD protection, level shifter and backdrive protection
Rev. 3 — 7 January 2011
Product data sheet
1. General description
The IP4791CZ12 is designed to protect mobile High-Definition Multimedia
Interface (HDMI) transmitter interfaces. It includes level shifting for the Data Display
Channel (DDC), Consumer Electronic Control (CEC), hot plug signal and backdrive
protection. In addition, all signals are protected by high-level ElectroStatic
Discharge (ESD) protection diodes.
The level shifting function is required to protect the I/Os against overvoltages when the
transmitter operates at a supply voltage lower than the external devices. The IP4791CZ12
contains active buffers to provide the level shifting function, hot plug detect input and the
CEC pull-up current source.
The ESD protection diodes provide protection from ESD voltages up to
±8
kV, according
to IEC 61000-4-2, level 4.
2. Features and benefits
HDMI 1.3 compliant
Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen
and antimony (Dark Green compliant)
Robust ESD protection without degradation after multiple ESD strikes
Low leakage even after several hundred ESD discharges
Bidirectional level shifting buffer provided for DDC clock and data channels
Backdrive protection
Power management
CEC pull-up current source and level shifting buffer
Hot plug detect module with pull-down resistor
Matched 0.4 mm trace spacing for HDMI type C connector
3. Applications
The IP4791CZ12 can be used with a range of HDMI transmitter devices including:
Personal computer
Notebook
Mobile phone
DV camcorder
Digital still camera
MP3 player
NXP Semiconductors
IP4791CZ12
HDMI ESD protection, level shifter and backdrive protection
4. Ordering information
Table 1.
Ordering information
Package
Name
IP4791CZ12
HXSON12
Description
plastic, thermal enhanced extremely thin small outline package; no leads;
12 terminals; body 2.1
×
2.5
×
0.5 mm
Version
SOT1156-1
Type number
5. Functional diagram
ESD rail 5.0 V
Enable
1.8 V
ESD rail 5.0 V
Enable
1.8 V
1.85 kΩ
3.6 kΩ
1.85 kΩ
3.6 kΩ
DDC data
(connector)
DDC data
(system)
DDC clock
(connector)
DDC clock
(system)
ESD rail 5.0 V
1.8 V
ESD rail 5.0 V
Enable
1.8 V
3V3
10 kΩ
26
kΩ
Active
100 kΩ
Enable
CEC out
(connector)
CEC in
(system)
ESD rail 5.0 V
1.8 V
ESD rail
HDMI_5V0_IN
HDMI_5V0_OUT
Hot plug in
100 kΩ
Hot plug out
100 kΩ
001aak735
Fig 1.
Functional diagram
IP4791CZ12
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 January 2011
2 of 17
NXP Semiconductors
IP4791CZ12
HDMI ESD protection, level shifter and backdrive protection
6. Pinning information
6.1 Pinning
CEC_IN 1
DDC_CLK_IN 2
DDC_DAT_IN 3
V
CC_LOW
4
HDMI_5V0_IN 5
HOTPLUG_DET_OUT 6
GND
12 CEC_OUT
11 DDC_CLK_OUT
10 DDC_DAT_OUT
9 ACTIVE
8 HDMI_5V0_OUT
7 HOTPLUG_DET_IN
001aak734
Fig 2.
Pin configuration (transparent top view)
6.2 Pin description
Table 2.
Symbol
CEC_IN
DDC_CLK_IN
DDC_DAT_IN
V
CC_LOW
HDMI_5V0_IN
HOTPLUG_DET_OUT
HOTPLUG_DET_IN
HDMI_5V0_OUT
ACTIVE
DDC_DAT_OUT
DDC_CLK_OUT
CEC_OUT
GND
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Pad
Description
CEC system side
DDC clock system side
DDC data system side
supply voltage, low voltage side for level shifting
5 V line from main supply
hot plug detect system side
hot plug detect connector side
5 V line to HDMI connector
power saving mode
DDC data connector side
DDC clock connector side
CEC connector side
ground
IP4791CZ12
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 January 2011
3 of 17
NXP Semiconductors
IP4791CZ12
HDMI ESD protection, level shifter and backdrive protection
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
ESD
electrostatic discharge
voltage
Conditions
signal pins to ground
at HDMI/DVI connector side
all pins
all pins
V
CC
V
I
P
tot
supply voltage
input voltage
total power dissipation
ACTIVE = HIGH;
DDC operating at 100 kHz, 50 % duty cycle;
CEC operating at 1 kHz, 50 % duty cycle
disable: HDMI cable not connected;
ACTIVE = LOW, DDC bus in Idle mode
T
stg
T
amb
[1]
[2]
[3]
[4]
[4]
[1]
[2]
[3]
Min
-
-
-
Max
±10
±200
±2
Unit
kV
V
kV
V
V
mW
GND
−
0.5 5.5
GND
−
0.5 5.5
-
30
-
−55
−40
0.2
+125
+85
mW
°C
°C
storage temperature
ambient temperature
IEC 61000-4-2, level 4, contact discharge.
Machine Model (MM) according to JESD22-A115-A.
Human Body Model (HBM) according to JESD22-A-J114D.
Including the current through the internal pull-up resistors.
8. Characteristics
Table 4.
Supplies
GND = 0 V; T
amb
= 25
°
C; unless otherwise specified.
Symbol
V
CC(5V0)
V
CC(1V8)
Parameter
supply voltage (5.0 V)
supply voltage (1.8 V)
Conditions
Min
4.5
1.62
Typ
5.0
1.8
Max
5.5
3.63
Unit
V
V
Table 5.
Static characteristics
V
CC(5V0)
= 5.0 V; V
CC(1V8)
= 1.8 V; GND = 0 V; T
amb
= 25
°
C; unless otherwise specified.
Symbol
R
dyn
Parameter
dynamic resistance
positive transient
negative transient
V
CL(ch)trt(pos)
positive transient channel V
ESD
= 8 kV, t
p
= 100 ns
clamping voltage
ACTIVE
V
IH
V
IL
R
pd
HIGH-level input voltage
LOW-level input voltage
pull-down resistance
[3]
[2]
Conditions
[1]
Min
Typ
Max
Unit
HDMI_5V0_OUT
-
-
-
0.6
0.4
8.0
-
-
-
Ω
Ω
V
1.2
-
60
-
-
100
-
0.8
140
V
V
kΩ
IP4791CZ12
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 January 2011
4 of 17
NXP Semiconductors
IP4791CZ12
HDMI ESD protection, level shifter and backdrive protection
Table 5.
Static characteristics
…continued
V
CC(5V0)
= 5.0 V; V
CC(1V8)
= 1.8 V; GND = 0 V; T
amb
= 25
°
C; unless otherwise specified.
Symbol
V
IH
V
IL
V
IK
V
OL
V
OH
C
IO
Parameter
HIGH-level input voltage
LOW-level input voltage
input clamping voltage
HIGH-level output voltage
input/output capacitance
V
CC(5V0)
= 0 V;
V
CC(1V8)
= 0 V;
V
bias
= 2.5 V;
AC input = 3.5 V
(p-p)
;
f = 100 kHz
I
I
=
−18
mA
[4]
[4]
Conditions
Min
0.5
×
V
CC(5V0)
−0.5
-
-
-
Typ
-
-
−1.0
100
8
Max
5.5
0.3
×
V
CC(5V0)
-
200
10
Unit
V
V
V
mV
pF
DDC buffer - connector side (pin 10 and pin 11)
[3]
LOW-level output voltage internal pull-down current
V
CC(5V0)
−
0.02 -
V
CC(5V0)
+ 0.02 V
R
pu
V
IH
V
IL
V
IK
V
OL
V
OH
C
IO
pull-up resistance
HIGH-level input voltage
LOW-level input voltage
input clamping voltage
LOW-level output voltage
HIGH-level output voltage
input/output capacitance
V
CC(5V0)
= 0 V;
V
CC(1V8)
= 0 V;
V
bias
= 2.5 V;
AC input = 3.5 V
(p-p)
;
f = 100 kHz
[4]
[4]
1.6
1.8
2.0
-
-
kΩ
V
V
DDC buffer - system side (pin 2 and pin 3)
[3]
0.26
×
V
CC(1V8)
-
-
I
I
=
−18
mA
-
-
-
-
−1.0
-
6
0.20
×
V
CC(1V8)
V
0.28
×
V
CC(1V8)
V
V
CC(1V8)
+ 0.02 V
8
pF
V
CC(1V8)
−
0.02 -
R
pu
CEC_OUT
[3]
V
IH
V
IL
V
OH
V
OL
C
IO
pull-up resistance
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage I
OL
= 1.5 mA
input/output capacitance
V
CC(5V0)
= 0 V;
V
CC(1V8)
= 0 V;
V
bias
= 2.5 V;
AC input = 3.5 V
(p-p)
;
f = 100 kHz
[4]
3.2
2.0
-
2.88
-
-
3.65
-
-
3.3
100
8
4.1
-
0.80
3.63
200
10
kΩ
V
V
V
mV
pF
R
pu
pull-up resistance
23.4
26.0
28.6
kΩ
IP4791CZ12
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 January 2011
5 of 17
PCB Design
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