WINBOND
ISA I/O
W83977EF
W83977EG
W83977EF-AW/W83977EG-AW
Revision History
PAGES
DATES
VERSION
VERSION
ON WEB
MAIN CONTENTS
1
2
3
4
n.a.
P86~P110
n.a.
12/30/03
03/07/03
04/25/03
04/25/06
Remove W83977CTF Part
Update the new version on web
Add Chapter 10 Configuration Register
Add Pb-free part no:W83977EG
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
-I-
Publication Release Date: Apr. 2006
Revision 1.2
W83977EF-AW/W83977EG-AW
Tables of Contents-
1.
2.
3.
4.
GENERAL DESCRIPTION ......................................................................................................... 5
FEATURES ................................................................................................................................. 6
PIN CONFIGURATION ............................................................................................................... 8
PIN DESCRIPTION.................................................................................................................... 9
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.
5.1
Host Interface ................................................................................................................. 9
General Purpose I/O Port ............................................................................................. 11
Serial Port Interface ...................................................................................................... 11
Infrared Interface .......................................................................................................... 12
Multi-Mode Parallel Port ............................................................................................... 13
FDC Interface ............................................................................................................... 17
KBC Interface................................................................................................................ 18
POWER PINS ............................................................................................................... 18
ACPI Interface............................................................................................................... 18
W83977EF/EG FDC ..................................................................................................... 19
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
AT interface ..................................................................................................................19
FIFO (Data) ..................................................................................................................19
Data Separator .............................................................................................................20
Write Precompensation ................................................................................................20
Perpendicular Recording Mode ....................................................................................20
FDC Core .....................................................................................................................21
FDC Commands...........................................................................................................21
Status Register A (SA Register) (Read base address + 0)...........................................32
Status Register B (SB Register) (Read base address + 1)...........................................34
Digital Output Register (DO Register) (Write base address + 2) ..................................36
Tape Drive Register (TD Register) (Read base address + 3).......................................36
Main Status Register (MS Register) (Read base address + 4).....................................37
Data Rate Register (DR Register) (Write base address + 4) ........................................37
FIFO Register (R/W base address + 5) ........................................................................39
Digital Input Register (DI Register) (Read base address + 7).......................................41
Configuration Control Register (CC Register) (Write base address + 7) ......................42
FDC FUNCTIONAL DESCRIPTION ......................................................................................... 19
5.2
Register Descriptions.................................................................................................... 32
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
6.
UART PORT ............................................................................................................................. 44
6.1
6.2
Universal Asynchronous Receiver/Transmitter (UART A, UART B) ............................ 44
Register Address .......................................................................................................... 44
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
UART Control Register (UCR) (Read/Write) ................................................................44
UART Status Register (USR) (Read/Write) ..................................................................47
Handshake Control Register (HCR) (Read/Write) ........................................................48
Handshake Status Register (HSR) (Read/Write)..........................................................48
UART FIFO Control Register (UFR) (Write only)..........................................................49
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W83977EF-AW/W83977EG-AW
6.2.6
6.2.7
6.2.8
6.2.9
Interrupt Status Register (ISR) (Read only) ..................................................................50
Interrupt Control Register (ICR) (Read/Write) ..............................................................51
Programmable Baud Generator (BLL/BHL) (Read/Write).............................................51
User-defined Register (UDR) (Read/Write) ..................................................................52
7.
PARALLEL PORT .................................................................................................................... 53
7.1
7.2
Printer Interface Logic................................................................................................... 53
Enhanced Parallel Port (EPP) ...................................................................................... 54
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
Data Swapper...............................................................................................................55
Printer Status Buffer .....................................................................................................55
Printer Control Latch and Printer Control Swapper.......................................................56
EPP Address Port ........................................................................................................56
EPP Data Port 0-3 ........................................................................................................57
Bit Map of Parallel Port and EPP Registers..................................................................57
EPP Pin Descriptions ...................................................................................................58
EPP Operation .............................................................................................................58
ECP Register and Mode Definitions .............................................................................59
Data and ecpAFifo Port ................................................................................................60
Device Status Register (DSR) ......................................................................................60
Device Control Register (DCR).....................................................................................61
CFIFO (Parallel Port Data FIFO) Mode = 010 ..............................................................62
ECPDFIFO (ECP Data FIFO) Mode = 011...................................................................62
TFIFO (Test FIFO Mode) Mode = 110..........................................................................62
CNFGA (Configuration Register A) Mode = 111...........................................................62
CNFGB (Configuration Register B) Mode = 111...........................................................62
ECR (Extended Control Register) Mode = all ...............................................................63
Bit Map of ECP Port Registers .....................................................................................64
ECP Pin Descriptions ...................................................................................................65
ECP Operation .............................................................................................................66
FIFO Operation ............................................................................................................66
DMA Transfers .............................................................................................................67
Programmed I/O (NON-DMA) Mode.............................................................................67
7.3
Extended Capabilities Parallel (ECP) Port ................................................................... 59
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.3.14
7.3.15
7.3.16
7.4
7.5
8.
8.1
8.2
8.3
8.4
8.5
Extension FDD Mode (EXTFDD).................................................................................. 67
Extension 2FDD Mode (EXT2FDD).............................................................................. 67
Output Buffer................................................................................................................. 68
Input Buffer ................................................................................................................... 68
Status Register ............................................................................................................. 69
Commands.................................................................................................................... 70
Hardware GATEA20/Keyboard Reset Control Logic................................................... 71
8.5.1
8.5.2
KB Control Register (Logic Device 5, CR-F0)...............................................................71
Port 92 Control Register (Default Value = 0x24) ..........................................................72
KEYBOARD CONTROLLER .................................................................................................... 68
-III-
Publication Release Date: Apr. 2006
Revision 1.2
W83977EF-AW/W83977EG-AW
8.6
OnNow / Security Keyboard and Mouse Wake-Up ...................................................... 73
8.6.1
8.6.2
8.6.3
Keyboard Wake-Up Function........................................................................................73
Keyboard Password Wake-Up Function .......................................................................73
Mouse Wake-Up Function ............................................................................................73
9.
GENERAL PURPOSE I/O......................................................................................................... 74
9.1
9.2
Basic I/O functions........................................................................................................ 76
Alternate I/O Functions ................................................................................................. 78
9.2.1
9.2.2
9.2.3
9.2.4
Interrupt Steering..........................................................................................................78
Watch Dog Timer Output..............................................................................................78
Power LED ...................................................................................................................79
General Purpose Address Decoder..............................................................................79
10.
PLUG AND PLAY CONFIGURATION ...................................................................................... 80
10.1
Compatible PnP............................................................................................................ 80
10.1.1 Extended Function Registers........................................................................................80
10.1.2 Extended Functions Enable Registers (EFERs) ...........................................................81
10.1.3 Extended Function Index Registers (EFIRs), Extended Function Data
Registers(EFDRs) .......................................................................................................................81
10.2
Configuration Sequence ............................................................................................... 81
10.2.1
10.2.2
10.2.3
10.2.4
Enter the extended function mode................................................................................81
Configurate the configuration registers.........................................................................82
Exit the extended function mode ..................................................................................82
Software programming example...................................................................................82
11.
12.
ACPI REGISTERS FEATURES................................................................................................ 83
CONFIGURATION REGISTER ................................................................................................ 84
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
Chip (Global) Control Register ..................................................................................... 84
Logical Device 0 (FDC)................................................................................................. 90
Logical Device 1 (Parallel Port) .................................................................................... 94
Logical Device 2 (UART A)¢) ....................................................................................... 95
Logical Device 3 (UART B)........................................................................................... 95
Logical Device 5 (KBC)................................................................................................. 97
Logical Device 7 (GP I/O Port I) ................................................................................... 98
Logical Device 8 (GP I/O Port II) ................................................................................ 101
Logical Device A (ACPI) ............................................................................................. 105
Absolute Maximum Ratings ........................................................................................ 112
DC CHARACTERISTICS............................................................................................ 112
AC Characteristics ...................................................................................................... 116
13.3.1
13.3.2
13.3.3
13.3.4
FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. ..............................................116
UART/Parallel Port .....................................................................................................118
Parallel Port Mode Parameters...................................................................................118
EPP Data or Address Read Cycle Timing Parameters...............................................119
13.
SPECIFICATIONS .................................................................................................................. 112
13.1
13.2
13.3
-IV-
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