PLL Based Clock Driver, 672 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16
Parameter Name | Attribute value |
Is it lead-free? | Lead free |
Is it Rohs certified? | conform to |
Maker | IDT (Integrated Device Technology) |
Parts packaging code | SOIC |
package instruction | SOP, |
Contacts | 16 |
Reach Compliance Code | compliant |
series | 672 |
Input adjustment | STANDARD |
JESD-30 code | R-PDSO-G16 |
JESD-609 code | e3 |
length | 9.9 mm |
Logic integrated circuit type | PLL BASED CLOCK DRIVER |
Number of functions | 1 |
Number of inverted outputs | |
Number of terminals | 16 |
Actual output times | 4 |
Maximum operating temperature | 85 °C |
Minimum operating temperature | -40 °C |
Output characteristics | 3-STATE |
Package body material | PLASTIC/EPOXY |
encapsulated code | SOP |
Package shape | RECTANGULAR |
Package form | SMALL OUTLINE |
Peak Reflow Temperature (Celsius) | 260 |
Certification status | Not Qualified |
Same Edge Skew-Max(tskwd) | 0.3 ns |
Maximum seat height | 1.75 mm |
Maximum supply voltage (Vsup) | 5.5 V |
Minimum supply voltage (Vsup) | 3.13 V |
Nominal supply voltage (Vsup) | 3.3 V |
surface mount | YES |
technology | CMOS |
Temperature level | INDUSTRIAL |
Terminal surface | MATTE TIN |
Terminal form | GULL WING |
Terminal pitch | 1.27 mm |
Terminal location | DUAL |
Maximum time at peak reflow temperature | 30 |
width | 3.9 mm |
minfmax | 135 MHz |
Base Number Matches | 1 |