number of wait states (0 to 63), programmable postread/post-
write delay (0 to 31), supports external wait state generation,
supports Intel and Motorola style peripherals
– Write protect capability per chip select
– Programmable bus transaction timer generates warm reset
when counter expires
– Supports up to 64MB of memory per chip select
◆
DMA Controller
– 9 DMA channels: two channels for each of the two Ethernet
interfaces (transmit/receive), two channels for PCI (PCI to
Memory and Memory to PCI), two channels for security engine
(input/output), one channel for the hardware random number
generator
– Provides flexible descriptor based operation
– Supports unaligned transfers (i.e., source or destination
address may be on any byte boundary) with arbitrary byte
length
◆
General Purpose Peripherals
– Serial port compatible with 16550 Universal Asynchronous
Receiver Transmitter (UART)
– Three general purpose 32-bit counter/timers
– Interrupt Controller
– Serial Peripheral Interface (SPI) supporting host mode
– 16 general purpose I/O (GPIO) pins which can be configured
as interrupt sources
◆
System Features
– JTAG Interface (IEEE Std. 1149.1 compatible)
– 256 pin CABGA package
– 2.5V core supply and 3.3V I/O supply
CPU Execution Core
The RC32365 is built around the RC32300 32-bit high performance
microprocessor core. The RC32300 implements the enhanced MIPS-II
ISA and helps meet the real-time goals and maximize throughput of
communications and consumer systems by providing capabilities such
as a prefetch instruction, multiple DSP instructions, and cache locking.
The instruction set is largely compatible with the MIPS32 instruction set,
allowing the customer to select from a broad range of software and
development tools. Cache locking guarantees real-time performance by
holding critical code and parameters in the cache for immediate avail-
ability. The microprocessor also implements an on-chip MMU with a
TLB, making the it fully compliant with the requirements of real time
operating systems.
Security Engine
The RC32365 incorporates an on-chip security engine that has been
designed to accelerate IPSec performance and minimize the amount of
performance required by the CPU to process secure packet traffic. The
engine includes hardware support for the DES, 3DES, and AES encryp-
tion algorithms and the MD5 and SHA1 hash functions. The engine also
supports hardware-assisted packet processing for the various modes of
IPSec, including AH, ESP, and AH+ESP tunnel and transport modes.
Two dedicated DMA channels are used to transfer data to and from the
security engine, allowing the CPU to work on other tasks during this
time.
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*Notice: The information in this document is subject to change without notice
March 17, 2003
RC32365
PCI Interface
The PCI interface on the RC32365 is compatible with version 2.2 of
the PCI specification. An on-chip arbiter supports up to three external
bus masters, supporting both fixed priority and rotating priority arbitra-
tion schemes. The RC32365 can support both satellite and host PCI
configurations, enabling it to act as a slave controller for a PCI add-in
card application, or as the primary PCI controller in the system. The PCI
interface can be operated synchronously or asynchronously to the other
I/O interfaces on the RC32365 device.
PCMCIA Interface
The RC32365 provides a "glueless" connection to a single PCMCIA
I/O device via the memory and peripheral device controller. The
PCMCIA interface allows the RC32365 to connect to various types of I/O
peripherals including fax modems, storage devices, and wireless LAN
chipsets. The RC32365 implementation provides a maximum
throughput of 160 Mbps through the 16-bit wide interface as specified by
the PCMCIA 2.1 Standard.
Ethernet Interface
The RC32365 has two Ethernet Channels supporting 10Mbps and
100Mbps speeds and provides a standard media independent interface
(MII) off-chip, allowing a wide range of external devices to be connected
efficiently.
Memory and I/O Controller
The RC32365 incorporates a flexible memory and peripheral device
controller providing direct support for SDRAM, Flash ROM, SRAM,
PCMCIA, and other I/O devices. It can interface directly to 8-bit boot
ROM for a very low cost system implementation. It also offers various
trade-offs in cost / performance for the main memory architecture. The
timers implemented on the RC32365 satisfy the requirements of most
real time operating systems.
DMA Controller
The DMA controller off-loads the CPU core from moving data among
the on-chip interfaces, external peripherals, and memory. The DMA
controller supports scatter / gather DMA with no alignment restrictions,
appropriate for communications and graphics systems.
Enhanced JTAG Interface
For system debugging, the RC32300 CPU core includes an
Enhanced JTAG (EJTAG) interface which operates in Run-Time Mode.
Revision History
March 17, 2003:
Initial publication.
Thermal Considerations
The RC32365 consumes less than 2.9 W peak power. It is guaran-
teed in a ambient temperature range of 0° to +70° C for commercial
temperature devices and - 40° to +85° for industrial temperature
devices.
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*Notice: The information in this document is subject to change without notice
March 17, 2003
RC32365
Pin Description Table
The following table lists the functions of the pins provided on the RC32365. Some of the functions listed may be multiplexed onto the same pin
(indicated as alternate functions).
To define the active polarity of a signal, a suffix will be used. Signals ending with an “N” should be interpreted as being active, or asserted, when at
a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one
(high) level.
Signal
Type
Name/Description
Memory and Peripheral Bus
BDIRN
O
External Buffer Direction.
Memory and peripheral bus external data bus buffer direction control.
If the RC32365 memory and peripheral bus is connected to the A side of a transceiver such as an
IDT74FCT245, then this pin may be directly connected to the direction control (e.g., BDIR) pin of
the transceiver.
External Buffer Enable.
These signals provide output enable control for external buffers on the
memory and peripheral data bus.
Byte Write Enables.
These signals are memory and peripheral bus byte write enable signals.
BWEN[0] corresponds to byte lane MDATA[7:0]
BWEN[1] corresponds to byte lane MDATA[15:8]
BWEN[2] corresponds to byte lane MDATA[23:16]
BWEN[3] corresponds to byte lane MDATA[31:24]
Chip Selects.
These signals are used to select an external device on the memory and peripheral
bus.
Address Bus.
22-bit memory and peripheral bus address bus.
MADDR[25:22] are available as GPIO[5:2] alternate functions.
Data Bus.
32-bit memory and peripheral data bus. During a cold reset, bits 0 through 16 of this
data bus function as inputs that are used to load the boot configuration vector.
Output Enable.
This signal is asserted when data should be driven by an external device on the
memory and peripheral bus.
Read Write.
This signal indicates whether the transaction on the memory and peripheral bus is a
read transaction or a write transaction. A high level indicates a read from an external device. A
low level indicates a write to an external device.
Wait or Transfer Acknowledge.
When configured as wait, this signal is asserted during a mem-
ory and peripheral bus transaction to extend the bus cycle. When configured as a transfer
acknowledge, this signal is asserted during a transaction to signal the completion of the transac-
tion.
SDRAM Row Address Strobe.
Row address strobe asserted during memory and peripheral bus
SDRAM transactions.
SDRAM Column Address Strobe.
Column address strobe asserted during memory and periph-
eral bus SDRAM transactions.
SDRAM Chip Selects.
These signals are used to select SDRAM device(s) on the memory and
peripheral bus.
SDRAM Write Enable.
This signal is asserted during memory and peripheral bus SDRAM write
transactions.
SDRAM Clock Output.
This clock is used for all SDRAM memory and peripheral bus operations.
SDRAM Clock Input.
This clock input is typically a delayed version of SDCLKOUT. Data from the
SDRAMs is sampled using this clock.
Table 1 Pin Description (Part 1 of 6)
BOEN[1:0]
BWEN[3:0]
O
O
CSN[5:0]
MADDR[21:0]
MDATA[31:0]
OEN
RWN
O
O
I/O
O
O
WAITACKN
I
RASN
CASN
SDCSN[1:0]
SDWEN
SDCLKOUT
SDCLKINP
O
O
O
O
O
I
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*Notice: The information in this document is subject to change without notice
March 17, 2003
RC32365
Signal
General Purpose I/O
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SOUT
Alternate function: UART channel 0 serial output.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SINP
Alternate function: UART channel 0 serial input.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: MADDR[22]
Alternate function: Memory and Peripheral bus address bit 22 (output).
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: MADDR[23]
Alternate function: Memory and Peripheral bus address bit 23 (output).
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: MADDR[24]
Alternate function: Memory and Peripheral bus address bit 24 (output).
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: MADDR[25]
Alternate function: Memory and Peripheral bus address bit 25 (output).
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: RNGCLK
Alternate function: External random number generator clock input
The value of this pin may be used as a Counter Timer Clock input.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: SDCKENP
Alternate function: SDRAM clock enable output
The value of this pin may be used as a Counter Timer Clock input.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
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