White Electronic Designs
PCMCIA Flash Memory Card
FLV Series
PCMCIA Flash Memory Card
2 MEGABYTE through 40 MEGEBYTE (Intel/Sharp based)
FEATURES
■
Low cost High Density Linear Flash Card
■
Supports 3V or 5V only systems
■
x8/ x16 Data Interface
■
Based on Intel/Sharp FlashFile Components
■
Fast Read Performance
- 150ns @ 5V
- 200ns @ 3.3V
■
High Performance Random Writes
- 8µs Typical Word Write Time @ 5V
- 17µs Typical Word Write Time @ 3.3V
■
Automated Write and Erase Algorithms
- Command User Interface
■
100,000 Erase Cycles per Block
■
64K word symmetrical Block Architecture
■
PC Card Standard Type I Form Factor
The WEDC FLV series is based on Intel/Sharp Flash
memories.
Note:
Standard options include attribute memory. Cards without
attribute memory are available. Cards are also available with or without
a hardware write protect switch.
ARCHITECTURE OVERVIEW
WEDCs FLV series is designed to support from 2 to 20
of 8Mb or 16MB components, providing a wide range of
density options. Cards are based on the 28F008SC
(8Mb) and 28F016SC (16Mb) devices for 3.3V or 5V only
applications. Devices codes for the 28F008SC and the
28F016SC are: A6H and AAH respectively. Systems
should be able to recognize all the codes. Cards utilizing
the 8Mb components provide densities ranging from
2MB to 20MB in 2MB increments, cards utilizing 16Mb
components provide densities ranging from 4MB to
40MB in 4MB increments.
In support of the PC Card 95 standard for word wide
access, devices are paired. Therefore, the Flash array
is structured in 64K word (128kBytes) blocks. Write, read
and block erase operations can be performed as either
a word or byte wide operation . By multiplexing A
0
, CE
1
and CE
2
, 8-bit hosts can access all data on data lines
DQ
0
- DQ
7
.
The
FLA21-FLA28
series also supports the following
PCMCIA compatible register functions: Soft Reset via the
Configuration Option Register, Power Down (sleep mode)
via the Configuration and Status Register and monitoring
of Ready/Busy, Soft Reset and Power Down via the Card
Status Register (cards without attribute memory and
versions
FLV51-FLV58
do not have registers).
FLV51-
FLV58
do not support Ready/Busy and Reset signals.
The FLV series cards conform to the PC Card (PCMCIA)
and JEIDA standards, providing electrical and physical
compatibility. The PC Card form factor offers an industry
standard pinout and mechanical outline, allowing density
upgrades without system design changes.
WEDCs standard cards are shipped with WEDCs Logo.
Cards are also available with blank housings (no Logo).
The blank housings are available in both a recessed
(for label) and flat housing. Please contact your WEDC
sales representative for further information on Custom
artwork.
1
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
GENERAL DESCRIPTION
WEDCs FLV Series Flash memory cards offer high
density linear Flash solid state storage solutions for
code and data storage, high performance disk emulation
and execute in place (XIP) applications in mobile PC
and dedicated (embedded) equipment.
FLV series cards conform to the PCMCIA international
standard
The cards control logic provides the system interface
and controls the internal Flash memories. The card can
be read/written in byte-wide or word-wide mode which
allows for flexible integration into various systems.
Combined with file management software, such as
Flash Translation Layer (FTL), FLV Flash cards provide
removable high-performance disk emulation.
The FLV series offers low power modes controlled by
registers. Cards contain separate 2kB EEPROM memory
for Card Information Structure (CIS) which can be used
for easy identification of card characteristics.
June 2003 Rev. 5
ECO #16104
White Electronic Designs
BLOCK DIAGRAM
Device Pair (N/2 - 1)
Device (N-1)
Device (N-2)
PCMCIA Flash Memory Card
FLV Series
CSn
Array
Address
Bus
ADDRESS
BUFFER
ADDRESS BUS
A
1
-A
25
Control
Address
Bus
M Res
WL
RL
WH
RH
CSn
Device 3
Device 2
CS
1
CS0
Control Logic
PCMCIA Interface
WE
OE
CE
2
CE
1
Cn
C0
Ctrl
REG
A
0
WP
Device Pair 1
At/Reg enable
SR Clr
Reg Clr
SR
PD
Card
Management
Registers
Device Pair 0
Device 1
Device 0
CS
0
4000h
Vcc
WH
RH
DATA
BUS
Q
8
-Q
15
DATA
BUS
Q
0
-Q
7
WL
RL
0000h
attrib. mem
CIS
EEPROM 2kB
Vcc
control
Q
0
-Q
7
Vcc
I/O buffer
Device type
28F008SC
28F016SC
Manuf ID
89
H
89
H
Device ID
A6
H
AA
H
DATA
BUS
D
8
-D
1 5
DATA
BUS
D
0
-D
7
REGISTERS IN ATTRIBUTE MEMORY SPACE*
ADDRESS
4100h
4002h
4000h
REGISTER NAME
Status Register
Config. and Status Register
Configuration Option Register
CSR
C
ONFIGURATION
S
TATUS
R
EGISTER
: ADRS = 4002h W
RITE
O
NLY
Not Supported
D7
D2
D6
D5
D4
D3
PDwn
D2
Not Supported
D1
D0
* FLV51- FLV58 and cards without Attribute
Memory do not have registers.
Power Down, active High
1 = Place all memory devices in power down mode
0 = Normal Operation
Power On default = 0
COR
SR
LREQ
D6
D5
D4
Configuration Index
D3
D2
D1
D0
C
ONFIGURATION
O
PTION
R
EGISTER
: ADRS = 4000h W
RITE
O
NLY
SRES
D7
D7
S
TATUS
R
EGISTER
: ADRS = 4100h R
EAD
O
NLY
Not Supported
D7
D5
D6
SReset
D5
D4
PDwn
D3
Not Supported R/BSY
D2
D1
D0
D6
D5-D0
Soft Reset, active High
1 = Reset State
0 = End Reset State
Level Req (not supported)
Configuration index (not supported)
D3
D0
Represents the state of SRESET bit in COR (4000h)
1 = Reset
0 = Normal Operation
Power On default D5 = 0
Represents the state of Power Down bit (D2) in CSR (4002h)
1 = Power Down
Reflects the card's Ready/Busy signal (pin 16) driven by
memory components Ready/Busy outputs. This bit allows
software polling of the card's Ready/Busy status.
1 = Ready
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
2
White Electronic Designs
P
INOUT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal name
GND
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
CE
1
A
10
OE
A
11
A
9
A
8
A
13
A
14
WE
RDY/BSY
V
CC
V
PP
1
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
WP
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PCMCIA Flash Memory Card
FLV Series
LOW
LOW
LOW
LOW (4)
NC
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
HIGH
Signal name
GND
CD
1
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
CE
2
VS
1
RFU
RFU
A
17
A
18
A
19
A
20
A
21
V
CC
V
PP
2
A
22
A
23
A
24
A
25
VS
2
RST
Wait
RFU
REG
BVD
2
BVD
1
DQ
8
DQ
9
DQ
10
CD
2
GND
I/O
O
I/O
I/O
I/O
I/O
I
I
O
I
I
I
I
I
I
I
I
I
O
I
O
I
O
O
I/O
I/O
O
O
Function
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Reserved
Reserved
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
Extended Bus cycle
Reserved
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
Data bit 9
Data bit 10
Card Detect 2
Ground
Active
LOW
LOW
NC (2)
NC
NC
HIGH
Low (3)
(3)
(3)
LOW
Notes:
1. RDY/BSY signal is an Open drain type output, pull-up resistor on host side is required.
2. Wait, BVD
1
and BVD
2
are driven high for compatibility.
3. Shows density for which specified address bit is MSB. Higher order address bits are no connects (ie: 4MB A
21
is MSB A
22
-A
25
are NC).
4. NC - No Connection for
FLV51-FLV58
MECHANICAL
1.0mm
±
0.05
(0.039”)
Interconnect area
1.6mm
±
0.05
(0.063”)
10.0mm MIN
(0.400”)
3.0mm MIN
Substrate area
54.0mm
±
0.10
(2.126”)
1.0mm
±
0.05
(0.039”)
10.0mm MIN
(0.400”)
85.6mm
±
0.20
(3.370”)
3.3mm
±
T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
3
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
Symbol
A
0
- A
25
DQ
0
- DQ
15
CE
1
, CE
2
OE
WE
RDY/BSY(*)
Type
INPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name and Function
PCMCIA Flash Memory Card
FLV Series
C
ARD
S
IGNAL
D
ESCRIPTION
ADDRESS INPUTS:
A
0
through A
25
enable direct addressing of up to 64MB of memory on the
card. Signal A
0
is not used in word access mode. A
25
is the most significant bit
DATA INPUT/OUTPUT:
DQ
0
THROUGH DQ
15
constitute the bi-directional databus. DQ
15
is the MSB.
CARD ENABLE 1 AND 2:
CE
1
enables even byte accesses, CE
2
enables odd byte accesses.
Multiplexing A
0
, CE
1
and CE
2
allows 8-bit hosts to access all data on DQ
0
- DQ
7
.
OUTPUT ENABLE:
Active low signal gating read data from the memory card.
WRITE ENABLE:
Active low signal gating write data to the memory card.
READY/BUSY OUTPUT:
Indicates status of internally timed erase or program algorithms. A high
output indicates that the card is ready to accept accesses. A low output indicates that one or more
devices in the memory card are busy with internally timed erase or write activities.
CARD DETECT 1 and 2:
Provide card insertion detection. These signals are internally connected
to ground on the card. The host shall monitor these signals to detect card insertion (pulled-up on
host side).
WRITE PROTECT:
Write protect reflects the status of the Write Protect switch on the memory
card. WP set to high = write protected, providing internal hardware write lockout to the Flash
array. If card does not include optional write protect switch, this signal will be pulled low internally
indicating write protect = off.
PROGRAM/ERASE POWER SUPPLY:
Provides programming voltages for card. Not connected for
3.3V/5V only card.
CARD POWER SUPPLY:
5.0V for all internal circuitry
CARD GROUND
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
ATTRIBUTE MEMORY SELECT :
Active low signal, enables access to attribute memory space,
occupied by the Card Information Structure (CIS) and Card Registers.
RESET:
Active high signal for placing card in Power-on default state. Reset can be used as a
Power-Down control for the memory array.
WAIT:
This signal is pulled high internally for compatibility. No wait states are generated.
BATTERY VOLTAGE DETECT:
These signals are pulled high to maintain SRAM card compatibility.
VOLTAGE SENSE:
Notifies the host socket of the cards V
CC
requirements. VS
1
and VS
2
are
open to indicate a 5V card .
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD:
pin may be driven or left floating
CD
1
, CD
2
OUTPUT
WP
OUTPUT
V
PP
1
, V
PP
2
V
CC
GND
REG
RST
WAIT
BVD
1
, BVD
2
VS
1
, VS
2
RFU
NC
N.C.
(*) Signals not supported by FLV51-FLV58 (NC)
F
UNCTIONAL
T
RUTH
T
ABLE
READ function
Function Mode
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
WRITE function
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
H
H
H
L
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
X
X
Odd-Byte
Odd-Byte
X
Even-Byte
Odd-Byte
Even-Byte
X
X
L
L
L
L
X
X
X
X
X
X
Even-Byte
X
Even-Byte
X
CE
2
H
H
H
L
L
CE
1
H
L
L
L
H
A
0
X
L
H
X
X
OE
X
L
L
L
L
WE
X
H
H
H
H
REG
X
H
H
H
H
Common Memory
D
15
-D
8
High-Z
High-Z
High-Z
Odd-Byte
Odd-Byte
D
7
-D
0
High-Z
Even-Byte
Odd-Byte
Even-Byte
High-Z
REG
X
L
L
L
L
Attribute Memory
D
15
-D
8
High-Z
High-Z
High-Z
Not Valid
Not Valid
D
7
-D
0
High-Z
Even-Byte
Not Valid
Even-Byte
High-Z
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
4
White Electronic Designs
Operating Temperature TA (ambient)
Commercial
Industrial
Storage Temperature
Commercial
Industrial
Voltage on any pin relative to V
SS
V
CC
supply Voltage relative to V
SS
PCMCIA Flash Memory Card
FLV Series
A
BSOLUTE
M
AXIMUM
R
ATINGS
(1)
0°C to +60 °C
-40°C to +85°C
-30°C to +80 °C
-40°C to +85°C
-0.5V to V
CC
+0.5V
-0.5V to +7.0V
Note:
Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and functional operation at these or any other conditions
greater than those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
DC C
HARACTERISTICS
(1)
V
CC
= 3.3V/5V
Symbol
I
CCR
I
CCW
I
CCE
I
CCS
(CMOS)
Parameter
V
CC
Read Current
V
CC
Program Current
V
CC
Erase Current
V
CC
Standby Current
Density
(Mbytes)
All
All
All
2MB
20MB
4MB
40MB
28F008SC
28F016SC
28F008SC
28F016SC
Notes
3.3V V
CC
Typ
(3)
Max
10
12
60
40
5V V
CC
Typ
(3)
Max
20
35
75
50
60
420
60
420
230
230
Units
mA
mA
mA
µA
Test Conditions
V
CC
= V
CC
max
tcycle = 150ns, CMOS levels
2
2
50
400
50
400
200
200
V
CC
= V
CC
max
Control Signals = V
CC
Reset = V
SS
, CMOS levels
CMOS Test Conditions: V
CC
= 5V ± 5%, V
IL
= V
SS
± 0.2V, V
IH
= V
CC
± 0.2V
Notes:
1. All currents are RMS values unless otherwise specified. I
CCR
, I
CCW
and I
CCE
are based on Byte wide operations. For 16 bit operation values
are double.
2. Control Signals: CE
1
, CE
2
, OE, WE, REG.
3. Typical: V
CC
= 5V, T = +25°C.
Symbol
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
V
LKO
Parameter
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
CC
Erase/Program
Lock Voltage
Notes
1
1
1
1
1
1
1
Min
Max
±20
±20
Units
µA
µA
V
V
V
V
V
Test Conditions
V
CC
= V
CC
MAX
V
IN
=V
CC
or V
SS
V
CC
= V
CC
MAX
V
OUT
=V
CC
or V
SS
0
0.7xV
CC
V
CC
-0.4
2.0
0.8
V
CC
+0.5
0.4
V
CC
I
OL
= 3.2mA
I
OH
= -2.0mA
Notes:
1. Values are the same for byte and word wide modes for all card densities.
2. Exceptions: Leakage currents on CE
1
, CE
2
, OE, REG and WE will be < 500 µA when V
IN
= GND due to internal pull-up resistors.
Leakage currents on RST will be <150µA when V
IN
=V
CC
due to internal pull-down resistor.
5
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
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