7052S25GGI datasheet, PDF - EEWORLD Datasheet

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7052S25GGI: DescriptionFour-Port SRAM, 2KX8, 25ns, CMOS, CPGA108, 1.210 X 1.210 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-108; Categorystorage storage; File Size121KB，12 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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7052S25GGI Overview

Four-Port SRAM, 2KX8, 25ns, CMOS, CPGA108, 1.210 X 1.210 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-108

7052S25GGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	PGA
package instruction	PGA, PGA108,12X12
Contacts	108
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	25 ns
I/O type	COMMON
JESD-30 code	S-CPGA-P108
JESD-609 code	e3
length	30.48 mm
memory density	16384 bit
Memory IC Type	FOUR-PORT SRAM
memory width	8
Number of functions	1
Number of ports	4
Number of terminals	108
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA108,12X12
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Maximum seat height	5.207 mm
Maximum standby current	0.03 A
Minimum standby current	4.5 V
Maximum slew rate	0.36 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	30
width	30.48 mm
Base Number Matches	1

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HIGH-SPEED

2K x 8 FourPort

STATIC RAM

Features

◆

IDT7052S/L

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

High-speed access

– Commercial: 20/25/35ns (max.)

– Industrial: 25ns (max.)

– Military: 25/35ns (max.)

Low-power operation

– IDT7052S

Active: 750mW (typ.)

Standby: 7.5mW (typ.)

– IDT7052L

Active: 750mW (typ.)

Standby: 1.5mW (typ.)

True FourPort memory cells which allow simultaneous

access of the same memory locations

Fully asynchronous operation from each of the four ports:

P1, P2, P3, P4

Versatile control for write-inhibit: separate

BUSY

input to

control write-inhibit for each of the four ports

◆

Battery backup operation—2V data retention

TTL-compatible; single 5V (±10%) power supply

Available in 120 pin Thin Quad Flatpacks and 108 pin PGA

Military product compliant to MIL-PRF-38535 QML

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Description

The IDT7052 is a high-speed 2K x 8 FourPort™ Static RAM designed

to be used in systems where multiple access into a common RAM is

required. This FourPort Static RAM offers increased system performance

in multiprocessor systems that have a need to communicate in real time and

also offers added benefit for high-speed systems in which multiple access

is required in the same cycle.

The IDT7052 is also designed to be used in systems where on-chip

hardware port arbitration is not needed. This part lends itself to those

◆

Functional Block Diagram

R/W

I/O

0P1

-I/O

7P1

BUSY

PORT 1

ADDRESS

DECODE

LOGIC

PORT 2

ADDRESS

DECODE

LOGIC

PORT 4

ADDRESS

DECODE

LOGIC

PORT 3

ADDRESS

DECODE

LOGIC

COLUMN

I/O

COLUMN

I/O

R/W

I/O

0P4

-I/O

7P4

BUSY

0P1

- A

10P1

0P4

- A

10P4

MEMORY

ARRAY

0P2

- A

10P2

BUSY

I/O

0P2

-I/O

7P2

R/W

0P3

- A

10P3

BUSY

COLUMN

I/O

COLUMN

I/O

0P3

-I/O

7P3

R/W

2674 drw 01

JUNE 2018

DSC 2674/16

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