HSP50016
TM
Data Sheet
September 2000
File Number
3288.7
Digital Down Converter
The Digital Down Converter (DDC) is a single chip
synthesizer, quadrature mixer and lowpass filter. Its input
data is a sampled data stream of up to 16 bits in width and
up to a 75 MSPS data rate. The DDC performs down
conversion, narrowband low pass filtering and decimation to
produce a baseband signal.
The internal synthesizer can produce a variety of signal
formats. They are: CW, frequency hopped, linear FM up
chirp, and linear FM down chirp. The complex result of the
modulation process is lowpass filtered and decimated with
identical real filters in the in-phase (I) and quadrature (Q)
processing chains.
Lowpass filtering is accomplished via a High Decimation
Filter (HDF) followed by a fixed Finite Impulse Response
(FIR) filter. The combined response of the two stage filter
results in a -3dB to -102dB shape factor of better than 1.5.
The stopband attenuation is greater than 106dB. The
composite passband ripple is less than 0.04dB. The
synthesizer and mixer can be bypassed so that the chip
operates as a single narrow band low pass filter.
The chip receives forty bit serial commands as a control
input. This interface is compatible with the serial I/O port
available on most microprocessors.
The output data can be configured in fixed point or single
precision floating point. The fixed point formats are 16,
24, 32, or 38-bit, two’s complement, signed magnitude, or
offset binary.
The circuit provides an IEEE 1149.1 Test Access Port.
Features
• 75 MSPS Input Data Rate
• 16-Bit Data Input; Offset Binary or 2’s Complement
Format
• Spurious Free Dynamic Range Through Modulator
>102dB
• Frequency Selectivity: <0.006Hz
• Identical Lowpass Filters for I and Q
• Passband Ripple: <0.04dB
• Stopband Attenuation: >104dB
• Filter -3dB to -102dB Shape Factor: <1.5
• Decimation Factors from 32 to 131,072
• IEEE 1149.1 Test Access Port
• HSP50016-EV Evaluation Board Available
Applications
• Cellular Base Stations
• Smart Antennas
• Channelized Receivers
• Spectrum Analysis
• Related Products: HI5703, HI5746, HI5766 A/Ds
Ordering Information
PART
NUMBER
HSP50016JC-52
HSP50016JC-75
TEMP. RANGE
(
o
C)
0 to 70
0 to 70
PACKAGE
44 Ld PLCC
44 Ld PLCC
PKG.
NO.
N44.65
N44.65
Block Diagram
16
DATA
CLK
OUTPUT
FORMATTER
OUTPUT
Q
Q
HIGH DECIMATION
FILTER
LOW PASS FIR
FILTER
I
I
HIGH DECIMATION
FILTER
CONTROL
COS
SIN
LOW PASS FIR
FILTER
IQSTRB
CLK
CLK
R
CLK
4R
OR
CLK
2R
IQCLK
COMPLEX
SINUSOID
GENERATOR
TEST ACCESS
PORT/CTRL
TEST ACCESS
PORT
CLK
SER
3-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
©
Intersil Corporation 2000
HSP50016
Pinout
GND
44 LEAD PLCC
TOP VIEW
IQSTRT
IQCLK
CDATA
IQSTB
CCLK
CSTB
V
CC
6 5 4 3 2 1 44 43 42 41 40
V
CC
DATA6
DATA5
DATA4
DATA3
V
CC
GND
CLK
DATA2
DATA1
DATA0
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
GND
RESET
GND
V
CC
V
CC
TRST
TMS
TDO
TCK
V
CC
TDI
39
38
37
36
35
34
33
32
31
30
29
GND
DATA15
DATA14
DATA13
DATA12
GND
DATA11
DATA10
DATA9
DATA8
DATA7
Pin Description
NAME
V
CC
GND
DATA0-15
CLK
RESET
TYPE
-
-
I
I
I
+5V Power.
Ground.
Input Data Bus. Selectable between two's complement and offset binary. DATA0 is the LSB.
Clock for input data bus. f
S
is the frequency of CLK, which is also the input sample rate.
RESET initializes the internal state of the DDC. During RESET, all internal processing stops. RESET
facilitates the synchronization of multiple chips for Auto Three-State operation. If the Force bits in Control
Word 7 are inactive and the IEEE Test Access Port is in an Idle state, RESET causes the IQCLK, IQSTB,
I and Q outputs to go to a high impedance state.
All Control Registers are updated from their respective Control Buffer Registers on the third rising edge
of CLK after the deassertion of RESET. If RESET is deasserted t
RS
nanoseconds prior to the rising edge
of CLK, the internal reset will deassert synchronously. If t
RS
is violated, then the circuit contains a syn-
chronizer which will cause reset to be deasserted internally one or more clocks later.
An initial reset is required to guarantee proper operation of the DDC. Active low.
I
Q
IQCLK
IQSTB
IQSTRT
CDATA
CCLK
CSTB
CS
TCK
TMS
TDI
TDO
TRST
O
O
O
O
I
I
I
I
I
I
I
I
O
I
The I output has three modes: I data; I data followed by Q data; real data.
The Q output has two modes: Q data and the carry out of the Phase Adder.
IQ Clock: Bit or word clock for the I and Q outputs.
IQ Strobe: Beginning or end of word indicator for I and Q.
IQ Start: Initiates output data sequence. Active low.
Control Data: Port for control data input.
Control Data Clock: Control data input bit clock.
Control Data Strobe: Beginning of word indicator for control data.
Chip Select: Enables control data loading of DDC. Active low.
Test Clock: Bit Clock for IEEE 1149.1 Data. This signal should be either tied low or pulled high when the
TAP is not used.
Test Port Mode Select: This signal should be either left unconnected or pulled high when the TAP is not
used.
Test Data Input for IEEE Test Port: This signal should be either left unconnected or pulled high when the
TAP is not used.
Test Data Output for IEEE Test Port: This output will be in the high impedance state when the TAP is
not used.
Test Port Reset. Active Low. This signal should be tied low when the TAP is not used.
DESCRIPTION
3-2
CS
Q
I
DDC Functional Block Diagram
HDF
SECTION
SCALING
MULTIPLIER
FIR SECTION
MIXER
SECTION
+
SHIFTER
18
18
I
CLK
R
17
SHIFT
REGISTER
HDF
17
DATA
RAM
MULTIPLIER/
ACCUMULATOR
†
INPUT
FORMAT
†
HDF
SHIFT
CLK
17
†
HDF
DECIMATION
COUNTER PRELOAD (DCP)
22
COEFFICIENT
ROM
CLK
SER
= IQCLK
CLK
4R
3-3
SHIFTER
+
18
18
17
MULTIPLIER/
ACCUMULATOR
FORMATTER
HDF
DATA
RAM
SHIFT
REGISTER
SCALE
FACTOR
DATA0-15
16
INPUT
REGISTER
COS
17
SIN
17
Q
SIN/COS
GENERATOR
†
SCALING
MULTIPLIER
GAIN
†
WAIT FOR RAM FULL
†
OUTPUT FORMAT
†
TIME SLOT LENGTH
(PARALLEL
TO SERIAL
CONVERTER
AND BUFFER)
PHASE WORD
18
†
MIN PHASE INCR
PHASE
GENERATOR
†
DELTA PHASE INCR
†
PHASE OFFSET
†
MAX PHASE INCR
†
MODE
†
IQSTRB THREE-STATE CTRL
IQSTB
HSP50016
LOCAL OSCILLATOR
†
NUMBER OF OUTPUT BITS
†
OUTPUT SENSE
†
I FOLLOWED BY Q
†
TIME SLOT NUMBER
†
IQCLK POLARITY
†
IQCLK DUTY CYCLE
†
IQCLK DURATION
†
IQCLK THREE-STATE CTL
†
IQSTRB POLARITY
†
IQSTRB LOCATION
IQSTRT
0
†
I POLARITY AND THREE-STATE CTRL
†
Q POLARITY AND THREE-STATE CTRL
†
IQ CLK RATE
†
TEST ENABLE AND CONTROL SIGNALS
IQCLK
CS
1
1
CSTB
DECODER
2
PARAMETERS
2
TCLK
CDATA
†
CONTROL
TMS
IEEE 1149.1
TEST ACCESS PORT
TDI
TDO
CCLK
7
7
TRST
CLK
RESET
D
Q
D
Q
CONTROL CONTROL
BUFFERS REGISTERS
†
Indicates parameters from control registers.
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
HSP50016
Phase Generator Block Diagram
PHASE ACCUMULATOR
†
PHASE OFFSET
MUX
>
R
E
G
18
1
PHASE REGISTER
R
E
G
33
18
PHASE WORD
(TO THE
SIN/COS
GENERATOR)
0
>
33
+
+
-
†
MAXIMUM PHASE
INCREMENT
R
E
G
32
MUX SELECT 1
PHASE INCREMENT ACCUMULATOR
PHASE
INCREMENT
REGISTER
R
E
G
PHASE ADDER
CARRY OUT
>
INCREMENT
>
R
E
G
1
MUX
†
MINIMUM PHASE
32
2
>
MUX SELECT 0
†
DELTA PHASE
INCREMENT
>
R
E
G
32
0
ADDER /
SUBTRACTOR
CARRY OUT
≤
INITIALIZE
PHASE INCR.
TO MIN
INITIALIZE
PHASE INCR.
TO MAX
MUX SELECT 0
CONTROL
MUX SELECT 1
>
†
MODE
CONTROL
†
Indicates parameters set in Control Registers.
FIGURE 2. PHASE GENERATOR BLOCK DIAGRAM
Functional Description
The primary function of the DDC is to extract a narrow
frequency band of interest from a wideband input, convert that
band to baseband and output it in either a quadrature or real
form. This narrow band extraction is accomplished by down
converting and centering the band of interest at DC. The
conversion is done by multiplying the input data with a
quadrature sinusoid. A quadrature lowpass filter is applied to
the multiplier outputs. Identical real lowpass filters are
provided in the in-phase (I) and quadrature phase (Q)
processing branches. Each filtering chain consists of a
cascaded HDF and FIR filter, which extracts the band of
interest. During filtering, the signal is decimated by a rate
which is proportional to the output bandwidth. The bandwidth
of the resulting signal is the double sided passband width of
the lowpass filters. An Output Formatter manipulates the filter
output to provide the data in a variety of serial data formats.
3-4
ADD/SUBTRACT
HSP50016
Local Oscillator
Signal data clocked into the DATA0-15 input of the DDC is
multiplied by a quadrature sinusoid in the Mixer Section (see
Figure 1). The data input to the DDC is a 16-bit real data
stream which is sampled on the rising edges of CLK. It can
be in two's complement or offset binary format.
The input data is passed to a mixer, which is composed of
two real multipliers. One of these multiplies the input data
samples by the in-phase (cosine) component of the
quadrature sinusoid, and the other multiplies the input data
samples by the quadrature (sine) component. The in-phase
and quadrature data paths are designated I and Q
respectively. The sine and cosine are generated in the local
oscillator as shown in Figure 1.
The local oscillator is programmed to produce a quadrature
sinusoid with programmable frequency and phase. The
frequency can be constant (Continuous Wave - CW), linearly
increasing (up chirp), linearly decreasing (down chirp), or
linear up/down chirp. The initial phase of the waveform is set
by the phase offset.
The phase, frequency and chirp limits of the quadrature
sinusoid are controlled by the Phase Generator (Figure 2).
The output of the Phase Generator is an 18-bit phase word
that represents the current phase angle of the complex
sinusoid. The Phase Generator automatically increments the
phase angle by a preprogrammed amount on every rising
edge of CLK. Stepping the output phase from 0 through full
scale (2
18
- 1) steps the phase angle of the quadrature
sinusoid from 0 to (-2+2
-17
)π radians.
NOTE: The phase is
stepped in a clockwise (decreasing) direction to support
down conversion.
The frequency of the complex sinusoid is
determined by the number of clocks needed for the phase to
step though its full range of 2π radians. The required phase
increment for a given local oscillator frequency is calculated by:
Phase Increment
=
INT
[ (
f
C
⁄
f
S
)
2
]H
–
33
; 0
<
f
C
<
f
S
/2
f
C
=
(
Phase Incr
)
f
S
2
33
minimum phase increment is the phase step taken on every
clock. When the SIN/COS Generator is producing a chirped
sinusoid, the minimum phase increment is the smallest
phase step taken. Maximum phase increment is only used
during Chirped Modes; it is the largest allowable phase
increment. During Chirp Modes, the delta phase increment
is the difference between successive phase increments.
The four phase parameters are stored in their respective
registers in the Phase Generator. The Phase Register stores
the current phase angle. On the first clock following the
deassertion of RESET, the 18 MSBs of the Phase Register
are loaded from the Phase Offset Register. On every rising
edge of CLK thereafter, the output of the Phase Increment
Register is subtracted from the 32 LSBs of the current
phase. The 33-bit difference is stored back in the Phase
Register on the next CLK. The 18 most significant bits of the
Phase Register form the phase word, which is the input to
the SIN/COS Generator.
Figure 3 gives a graphic representation of the phase
parameters for the CW case. To understand their
interrelationships, the phase should be visualized as the
angle of a rotating vector. When the local oscillator in the
DDC is programmed to generate a CW waveform, the
multiplexers are configured so that the Minimum Phase
Increment is stored in the Phase Increment Register; this
value is subtracted from the output of the Phase Register on
every CLK and the difference becomes the new Phase
Register value. The Delta Phase Increment and Maximum
Phase Increment are ignored when generating a CW.
STARTING PHASE
+90
o
θ
INCR
(0)
(1)
(2)
±180
o
θ
OFFSET
θ
INCR
θ
INCR
θ
INCR
0
o
(EQ. 1)
where:
f
C
is the desired local oscillator frequency
f
S
is the input sampling frequency
Phase Increment is the Control Word Value (in Hex)
There are five parameters which control the Phase Generator:
Phase offset, minimum phase increment, maximum phase
increment, delta phase increment and Mode Control. These
values are programmed via Control Words 2, 3, and 4. Mode
Control is used to select the function of the other parameters.
The phase offset is the initial setting of the phase word going
to the SIN/COS Generator. Subsequent phases of the
sinusoid are calculated relative to this offset. The minimum
phase increment has two mode dependent functions: when
the SIN/COS Generator is forming a CW waveform, the
(3)
(4)
(5)
θ
INCR
-90
o
FIGURE 3. PHASE WORD PARAMETERS FOR CW CASE
In Up Chirp Mode the local oscillator generates a signal
with a linearly increasing frequency (Figure 4A). The Phase
Increment Register is initially loaded with the minimum
Phase Increment value; on every clock, the contents of the
Phase Increment Register is subtracted from the current
output of the Phase Register. Simultaneously, the Delta
3-5
京公网安备 11010802033920号
EEWORLD
