Micrel, Inc.
3.3V 28Mbps-2.5Gbps AnyRate
®
CLOCK AND DATA RECOVERY
SY87702L
SY87702L
FEATURES
■
3.3V power supply
■
Complies with Bellcore, ITU/CCITT and ANSI
specifications for applications such as OC-1, OC-3,
OC-12, OC-48*, and ATM
■
Compatible with FDDI, Gigabit Ethernet, Fibre
Channel, 2X Fibre Channel, SMPTE 259 and 292, and
proprietary applications
■
Low power
■
Clock and data recovery from 28Mbps up to 2.5Gbps
NRZ data stream
■
Selectable reference frequencies via programmable
multiplier
■
■
■
■
Differential PECL and CML high-speed serial outputs
Line receiver input: no external buffering needed
Link fault indication
100K ECL compatible I/O
DESCRIPTION
The SY87702L is a complete Clock Recovery and Data
retiming integrated circuit for data rates from 28Mbps up to
2.5Gbps NRZ. The device is ideally suited for SONET/SDH/
ATM, Fibre Channel, and Gigabit Ethernet applications, as
well as other high-speed data transmission applications.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming data
stream. The VCO center frequency is controlled by the
reference clock frequency and the selected divide ratio. On-
chip clock generation is performed through the use of a
frequency multiplier PLL and can be used as a Clock
Multiplier Unit (CMU). The integrated CMU can provide this
clock signal at the TCLK outputs. Additionally, the TCLK
output can be selected to provide a copy of the RCLK
frequency.
For SONET/SDH applications, the SY87702L includes a
Link Fault Detection circuit. This circuit, enabled by the output
of an optical module driving the CD input low, causes the
recovery PLL of the SY87702L to lock to the reference
clock's multiplied frequency under Loss-of-Signal conditions.
This low jitter clock is provided at the RCLK outputs and is
at the same frequency as that provided at the TCLK output.
■
Available in 64-Pin EP-TQFP package
■
Product obsolete. Use SY87721L for new designs
*Meets OC-48 Jitter Tolerance and Transfer
APPLICATIONS
■
Transponders and section repeaters
■
Multiplexer's: access, add drop (ADM), and terminal
(TM)
■
SONET/SDH/ATM: -based transmission systems,
modules, and test equipment
■
Terabit routers and broadband cross-connects
■
Fibre optic test equipment
■
HDTV switching and transmission
AnyRate
®
is a registered trademark of Micrel, Inc.
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
1
Rev.: D
Amendment: /0
Issue Date: July 2006
Micrel, Inc.
SY87702L
FUNCTIONAL DESCRIPTION
Clock Recovery
Clock Recovery, as shown in the block diagram,
generates a clock that is at the same frequency as the
incoming data bit rate at the Serial Data input. The clock is
phase aligned by a PLL so that it samples the data in the
center of the data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability, without incoming data, is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the multiplied frequency
of the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30µs data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
PIN NAMES
INPUTS
RDIN
±
[Serial Data Input]
– Differential PECL
This differential input accepts the receive serial data
stream. An internal receive PLL recovers the embedded
clock (RCLK) and data (RDOUT) information. The incoming
data rate can be within one of ten frequency ranges, or can
be one of five specific frequencies, depending on the state
of the FREQSEL and VCOSEL pins. The RDIN– pin has an
internal 75KΩ resistor tied to V
CC
.
REFCLK
±
[Reference Clock]
– Differential PECL
This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN input. The input frequency to
REFCLK is limited to 325MHz or less, depending on the
setting on the DIVSEL signals. The REFCLK– pin has an
internal 75KΩ resistor tied to V
CC
.
CD [Carrier Detect]
– PECL Input
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH, the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW, the
data on the RDIN input will be internally forced to a constant
LOW, the data output RDOUT will remain LOW, the Link
Fault Indicator output LFIN forced LOW, and the clock
recovery PLL forced to lock onto the clock frequency
generated from REFCLK.
VCOSEL1, VCOSEL2 [VCO Select]
– TTL Inputs
These inputs select the VCO frequency range via either
one of three wide-band PLLs, or a SONET/SDH specific
narrow-band PLL. Only the selected PLL is enabled. All
other PLL’s are disabled. Please refer to Table 1.
VCOSEL1
0
0
1
1
VCOSEL2
0
1
0
1
Table. 1
Choice
SONET/SDH
1.8 to 2.5GHz
1.25 to 1.8GHz
0.650 to 1.30GHz
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
5
京公网安备 11010802033920号
EEWORLD
