dge
gation
vice)
Gateway xChange field-hardened software
•
the CALISTO communication processor integrated with
•
Gateway xChange software provides:
• Packet voice
• Line echo cancellation with 16–128 ms tail length
- VAD/CNG
- Voice compression: G.711 µ-law/A-law PCM 64 Kbps, G.726
16/24/32/40 Kbps, G.729A/B 8 Kbps, G.729E 11.8 Kbps,
G.723.1/A 5.3/6.3 Kbps, G.728 16 Kbps
• Dynamic jitter buffer manager for all services
• Fax relay
- Fax synchronization
- T.38 relay and fax over AAL2
- Data pumps: V.17 14400 bps, V.29 9600 bps, V.27ter
• Data relay
- Data synchronization
- Data pumps: V.34 33600 bps, V.32bis/V.32 14400 bps,
V.22bis/V.22 2400 bps
• Signaling relay: DTMF, MF-R1, Type 1 Caller ID, and
CPM/CPG
•
•
Includes field-hardened Gateway xChange services.
•
HausWare Framework’s RTOS provides the ability to
dynamically configure the system for over 200 channels
of carrier class G.711 or 60 channels of full universal port
processing.
•
Enables toll-quality voice.
•
Open platform provides customers with the flexibility to
customize the solutions by adding their own unique
services.
Shorten product development time with CALISTO GUI-
based tools suite:
exibility to add to and to expand the API as
ed to CALISTO, or when new hardware devices
e.
•
Reference design platform and training is available for
• Industry-leading optimizing C compiler
• Assembler
• Linker
• Debugger with cycle-accurate simulator and profiler
• Unique multichannel, multiservice debug paradigm
• Remote debug capability
testing and customization projects.
the library objects into tables maintained by call
plications, or add system-specific data to the
they themselves become the table entries. The
ate addressing and state data to provide a flexible
a organization.
•
BCM1500/1510 chip
• Robust API
• 21 processing units per chip: 16 SpiceEngines™ and 5 RISC
processors
• 8 physical interfaces: 2 TDM ports, 2 SpiceBus ports, SDRAM
port, JTAG port, SPI serial boot port, and PLL port
• 19-mm, 239-ball ceramic fine-pitch BGA
• Reconfigurable-adaptive instruction sets
• Over 3.3 GMACs of signal processing power
• C compiler and robust Integrated Development Environment
(IDE) included
Master
Proc
TDM
CALISTO Architecture
Cluster Memory
Boot
Cluster
Proc
Cluster Memory
nted approach also lets the API manage state for
If users reset a CALISTO, all Channel Socket
ed with the CALISTO change state as well. This
ssists users in managing connections, and in
hot backup redundancy scheme.
Shared Memory
Cluster
Proc
SpiceEngine Array
Cluster Memory
Cluster
Proc
Spice
Engine
Cluster
Proc
Cluster Memory
Phone: 949-450-8700
FAX: 949-450-8710
Email: info@broadcom.com
Web: www.broadcom.com
SpiceBus
DRAM (optional)
BCM1510
N
Fax Relay
Data Relay
Conferencing
Service
AUX IN/OUT
AUX IN/OUT
CPM
CPG
DTMF/MFG
CDIS
G.723.1/A 5.3/6.3 kbps
G.728 16 kbps
Fax Relay
Jitter Buffer Manager
Fax Synchronization
Fax Modems
T.3x Relay
Tone Service
DTMF/MFD
V.2x/V.1x Data Pump
V.17 14400 bps
V.29 9600 bps
V.26ter 4800 bps
oot port provides a standard Serial Peripheral
I) running at up to 5 MHz.
test access port provides support for JTAG IEEE
G.711
Call
Descriminator
Service
V.21/CED/
CNG/V.18
V.21/CED/
CNG/V.18
Data Relay
Jitter Buffer Manager
Circuit
Interface
Service
G.165/168
Data Synchronization
G.711
Data Modems
Data Relay
V.3x/V.2x Data Pump
V.34 33600 bps
V.32bis/V.32 14400 bps
V.22bis/V.22 2400 bps
PLL provides core frequencies of up to 166 MHz.
bsystem
Gateway xChange VoP software in conjunction with the
CALISTO BCM1500/1510 enables the highest density
processing of voice/fax/data over packet networks in the
industry.
xChange Services
The Circuit Interface Service (PCM or AAL1) supports G.711
µ-law/A-law, hosts G.168 echo cancellation with 32/64/128 ms
tail lengths, detects and generates idle patterns, initializes linear
ingress and egress media buffers, stores ingress/egress history,
provides loopback towards circuit or packet network, provides
gain control on ingress/egress samples, and provides energy
measurement of ingress media.
The Call Discrimination Service (CDIS) hosts fax/modem/V.18
detection, allows detection events to be used by the supervisory
service to reconfigure the channel, and runs in either the ingress
or egress direction.
The Tone Service (PTE) detects DTMF, MF, and PTP tones, and
incorporates programmable tone generation in packet or TDM
direction, with features to support special tones like calling
cards.
The Conferencing Service transmits samples to another channel,
receives samples and sums with local data, and includes an
aggregation channel to provide support for larger conferences.
figure shows a CALISTO-based subsystem
dling an OC-3 (2016 DS0). Each CALISTO
wards the system interface, the SpiceBus, thus
e need for host-assisted DMA from shared
lowing the use of efficient aggregation devices,
s. Each SpiceBridge aggregates, in a single step,
a traffic from up to eight CALISTO devices
stem backplane. Broadcom provides several
piceBridge as flexible logic cores.
e Bridge in the preceding figure, the CALISTO
dependent Interface) Bridge, supports FPGA
of the MII to the CALISTO BCM1500/1510
chitecture. A device built around this logic core
eight BCM1500/1510s to a single MII interface.
Bridge enables the design of high density Voice
ms.
The Packet Voice Service (PVE) incorporates an
adaptable/configurable jitter buffer, vocoders, and VAD/CNG;
supports asymmetric encode/decode; provides G.711, G.726,
G.729A/B/E, G.728, G.723.1, AMR, and GSM/EFR algorithms,
with 5-ms packetizations for G.711, G.726, and G.278; allows
super-packetization of up to eight frames, reorders packets in the
jitter buffer, provides jitter buffer statistics, includes a packet loss
concealment algorithm, provides egress VAD for jitter buffer
adaptation control (in the absence of arriving SIDS) and for noise
level/spectrum matching; supports voice band data mode, with
clock drift compensation, for modem/fax pass-through.
O MII Bridge is integral to Broadcom’s
multiservice, carrier-access architecture. By
-side control and data flows, the bridge supports
tion of circuit-switched and packet-switched
Broadcom-supported Verilog block, the CALISTO
n be quickly reconfigured to meet changing
ements.
The Fax Relay Service accepts T.38 or AAL2 packet formats,
supports V.21, V.27ter, V.29, V.17 and V.33 data algorithms,
incorporates end-of-line spoofing for non-ECM calls and HDLC
spoofing for V.21 and ECM calls and supports both T.32 Data
Rate Management methods.
The Supervisory Service intercepts and filters events generated
by services, and provides a high-level control interface.
The Packet Interface Service supports either RTP/UDP/IP or
AAL1/AAL2 packet encapsulation, converts from internal
packet headers to protocol-specific headers, sends and receives
data on the packet interface, provides support for loopback
towards circuit or packet network.
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