Changes to Ordering Guide .......................................................... 24
3/05—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V
REF
= VDD, T
A
= –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input CMRR
Leakage Current
Input Impedance
ACCURACY
No Missing Codes
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error
2
, T
MIN
to T
MAX
Gain Error Temperature Drift
Offset Error
2
, T
MIN
to T
MAX
Offset Temperature Drift
Power Supply Sensitivity
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Signal-to-Noise and Distortion Ratio (SINAD)
Conditions
Min
14
0
−0.1
−0.1
Typ
Max
AD7942
Unit
Bits
V
V
V
dB
nA
IN+ − IN−
IN+
IN−
f
IN
= 250 kHz
T
A
= 25°C, acquisition phase
V
REF
VDD + 0.1
+0.1
65
1
See the Analog Input section
14
−0.7
−1
V
REF
= VDD = 5 V
VDD = 4.5 V to 5.5 V
VDD = 2.3 V to 4.5 V
VDD = 5 V ± 5%
VDD = 4.5 V to 5.5 V
VDD = 2.3 V to 4.5 V
Full-scale step
f
IN
= 20 kHz, V
REF
= 5 V
f
IN
= 20 kHz, V
REF
= 2.5 V
f
IN
= 20 kHz
f
IN
= 20 kHz
f
IN
= 20 kHz, V
REF
= 5 V
f
IN
= 20 kHz, V
REF
= 5 V, −60 dB input
f
IN
= 20 kHz, V
REF
= 2.5 V
0
0
±0.3
±0.4
0.33
±0.7
±1
±0.45
±0.75
±2.5
±0.1
+0.7
+1
±6
±3
±4.5
Bits
LSB
1
LSB
LSB
LSB
ppm/°C
mV
mV
ppm/°C
LSB
kSPS
kSPS
μs
dB
3
dB
dB
dB
dB
dB
dB
250
200
1.8
85
84
−100
−100
85
25
84
VDD + 0.3
50
2
2.5
84.5
83
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
0.5
250 kSPS, V
REF
= 5 V
V
μA
MHz
ns
VDD = 5 V
–0.3
0.7 × VIO
−1
−1
+0.3 × VIO
VIO + 0.3
+1
+1
V
V
μA
μA
Rev. C | Page 3 of 24
AD7942
Parameter
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Conditions
Min
Typ
Max
Data Sheet
Unit
V
OL
V
OH
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current
4, 5
Power Dissipation
I
SINK
= +500 μA
I
SOURCE
= −500 μA
Specified performance
Specified performance
VDD and VIO = 5 V, at 25°C
VDD = 2.5 V, 100 SPS throughput
VDD = 2.5 V, 100 kSPS throughput
VDD = 2.5 V, 200 kSPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 250 kSPS throughput
T
MIN
to T
MAX
Serial 14 bits straight binary
Conversion results available
immediately after
completed conversion
0.4
VIO − 0.3
2.3
2.3
1.8
1
1.25
1.25
2.5
3.6
5.5
VDD + 0.3
VDD + 0.3
50
2
4
5
12.5
+85
V
V
V
V
V
nA
μW
mW
mW
mW
mW
°C
TEMPERATURE RANGE
6
Specified Performance
1
2
−40
LSB means least significant bit. With a 5 V input range, 1 LSB = 305.2 μV.
See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3
All specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
With all digital inputs forced to VIO or GND as required.
5
During acquisition phase.
6
Contact Analog Devices, Inc., sales for an extended temperature range.
Rev. C | Page 4 of 24
Data Sheet
TIMING SPECIFICATIONS
AD7942
VDD = 4.5 V to 5.5 V
1
, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, T
A
= −40°C to +85°C.
Table 3.
Parameter
Conversion Time: CNV Rising Edge to Available Data
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO ≥ 4.5 V
VIO ≥ 3 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data-Valid Delay
VIO ≥ 4.5 V
VIO ≥ 3 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
CNV or SDI Low to SDO D13 MSB Valid (CS Mode)
VIO ≥ 4.5 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
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