a
FEATURES
IEC 687, Class 0.5 and Class 0.2 Accuracy
ANSI C12.1
IEC 1268, Requirements for Reactive Power
Configurable as Import/Export or Import Only
Simultaneous Measurement of:
Active Power and Energy—Import and Export
Reactive Power and Energy
Apparent Power
Power Factor for Individual Phases and Total Frequency
RMS Voltage for All Phases
RMS Current for All Phases
Harmonic Analysis for Voltage and Current
All Odd Harmonics up to 21st Order
Interface with a General Purpose Microcontroller
User-Friendly Calibration of Gain Offset and Phase and
Nonlinearity Compensation on CTs (Patent Pending)
Two Programmable Output E-Pulses
Programmable E-Pulse Constant from 1,000 Pulses/kWh
to 20,000 Pulses/kWh
15 kHz Sampling Frequency
Tamper-Proof Metering
Single 5 V Supply
GENERAL DESCRIPTION
SMPS
RESISTOR
BLOCK
SALEM Three-Phase
Electronic Energy Meter
ADSST-EM-3035
FUNCTIONAL BLOCK DIAGRAM
LCD DISPLAY
®
DSP
SPI BUS
C
ADC
BUTTONS
CT
CT
CT
ADSST-EM-3035
CHIPSET
FLASH
OPTO
RTC
RS-232
The ADSST-EM-3035 Chipset consists of a fast and accurate
6 channel, 16-bit sigma-delta analog-to-digital converter
ADSST-73360AR (ADC), an efficient digital signal processor
ADSST-2185KST-133 (DSP), and Metering Software. The
ADC and DSP are interfaced together to simultaneously acquire
voltage and current samples on all the three phases and perform
mathematically intensive computations to accurately calculate
the Powers, Energies, Instantaneous Quantities, and Harmonics.
The chipset could be interfaced to any general-purpose micropro-
cessor to develop state of the art polyphase or Tri-vector energy
metering solution in accordance with IEC 1036, IEC 687, or
ANSI C12.1.
All calibrations are done in digital domain and no trimming
potentiometers are required.
SALEM is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
ADSST-EM-3035
ADSST-2185KST-133 (DSP) SPECIFICATION
FEATURES
30 ns Instruction Cycle 33 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Three-Bus Architecture Allows Dual Operand Fetches
in Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby Power
Dissipation with 100 Cycle Recovery from Power-Down
Condition
Low Power Dissipation in Idle Mode
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
40 kBytes of On-Chip RAM, Configured as
8 KWords On-Chip Program Memory RAM and
8 KWords On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead TQFP
16-Bit Internal DMA Port for High Speed Access to On-
Chip Memory (Mode Selectable)
4 MBytes Byte Memory Interface for Storage of Data
Tables and Program Overlays
8-Bit DMA to Byte Memory for Transparent Program and
Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits Glueless System Design
(Mode Selectable)
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or through
Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port Emulator Interface Supports Debugging in Final Systems
GENERAL DESCRIPTION
The ADSST-2185KST-133 is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.
The ADSST-2185KST-133 combines the ADSP-2100 family
base architecture (three computational units, data address
generators, and a program sequencer) with two serial ports, a
16-bit internal DMA port, a byte DMA port, a programmable
timer, Flag I/O, extensive interrupt capabilities, and on-chip
program and data memory.
The ADSST-2185KST-133 integrates 40 kBytes of on-chip
memory configured as 8 Kwords (24-bit) of program RAM and
8 Kwords (16-bit) of data RAM. Power-down circuitry is also
provided to meet the low power needs of battery operated portable
equipment. The ADSST-2185KST-133 is available in a 100-lead
TQFP package.
In addition, the ADSST-2185KST-133 supports instructions
that include bit manipulations, bit set, bit clear, bit toggle, bit
test new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers, and global interrupt masking for increased flexibility.
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSST-2185KST-133 operates with a 25 ns
instruction cycle time. Every instruction can execute in a single
processor cycle.
The ADSST-2185KST-133’s flexible architecture and com-
prehensive instruction set allow the processor to perform
multiple operations in parallel. In one processor cycle, the
ADSST-2185KST-133 can:
•
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
This takes place while the processor continues to:
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal DMA port
Receive and/or transmit data through the byte DMA port
Decrement timer
POWER-DOWN
CONTROL
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
MEMORY
PROGRAM
SEQUENCER
16K 24
PROGRAM
MEMORY
16K 16
DATA
MEMORY
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT0
SPORT 1
TIMER
INTERNAL
DMA
PORT
HOST MODE
ADSP-2100 BASE
ARCHITECTURE
Figure 1. Functional Block Diagram
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ADSST-EM-3035
ARCHITECTURE OVERVIEW
The ADSST-2185KST-133 instruction set provides flexible
data moves and multifunction (one or two data moves with a
computation) instructions. Every instruction can be executed in
a single processor cycle. The ADSST-2185KST-133 assembly
language uses an algebraic syntax for ease of coding and read-
ability. A comprehensive set of development tools supports
program development.
Figure 1 is an overall block diagram of the ADSST-2185KST-133.
The processor contains three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with 40
bits of accumulation. The shifter performs logical and arithmetic
shifts, normalization, denormalization and derive exponent
operations.
The shifter can be used to efficiently implement numeric format
control including multiword and block floating-point representations.
The internal result (R) bus connects the computational units
so the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these com-
putational units. The sequencer supports conditional jumps,
subroutine calls, and returns in a single cycle. With internal loop
counters and loop stacks, the ADSST-2185KST-133 executes
looped code with zero overhead. No explicit jump instructions
are required to maintain loops.
Two data address generators (DAGs) provide addresses for simul-
taneous dual operand fetches from data memory and program memory.
Each DAG maintains and updates four address pointers. Whenever
the pointer is used to access data (indirect addressing), it is post-
modified by the value of one of four possible modify registers. A
length value may be associated with each pointer to implement
automatic modulo addressing for circular buffers.
Efficient data transfer is achieved with the use of five internal buses:
•
Program Memory Address (PMA) Bus
•
Program Memory Data (PMD) Bus
•
Data Memory Address (DMA) Bus
•
Data Memory Data (DMD) Bus
•
Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the two
data buses (PMD and DMD) share a single external data bus. Byte
memory space and I/O memory space also share the external buses.
Program memory can store both instructions and data, permitting
the ADSST-2185KST-133 to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSST-2185KST-133 can fetch an operand from program
memory and the next instruction in the same cycle.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with programmable
wait state generation. External devices can gain control of external
buses with bus request/grant signals (BR,
BGH,
and
BG).
One
execution mode (Go Mode) allows the ADSST-2185KST-133
to continue running from on-chip memory. Normal execution
mode requires the processor to halt while buses are granted.
The ADSST-2185KST-133 can respond to 11 interrupts.
There are up to six external interrupts (one edge-sensitive, two
level-sensitive, and three configurable) and seven internal inter-
rupts generated by the timer, the serial ports (SPORTs), the
Byte DMA port, and the power-down circuitry. There is also a
master
RESET
signal. The two serial ports provide a complete
synchronous serial interface with optional companding in hard-
ware and a wide variety of framed or frameless data transmit
and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSST-2185KST-133 provides up to 13 general purpose
flag pins. The data input and output pins on SPORT1 can be
alternatively configured as an input flag and an output flag. In
addition, eight flags are programmable as inputs or outputs, and
three flags are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register (TSCALE).
When the value of the count register reaches zero, an interrupt is
generated and the count register is reloaded from a 16-bit period
register (TPERIOD).
Serial Ports
The ADSST-2185KST-133 incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSST-2185KST-133
SPORTs. For additional information on Serial Ports, refer to
the
ADSP-2100 Family User’s Manual,
Third Edition.
•
SPORTs are bidirectional and have a separate, double-buffered
transmit and receive section.
•
SPORTs can use an external serial clock or generate their own
serial clock internally.
•
SPORTs have independent framing for the receive and transmit
sections. Sections run in a frameless mode or with frame synchro-
nization signals internally or externally generated. Frame
sync signals are active high or inverted, with either of two
pulsewidths and timings.
•
SPORTs support serial data word lengths from 3 to 16 bits and
provide optional A-law and M-law companding according to
CCITT recommendation G.711.
•
SPORT receive and transmit sections can generate unique
interrupts on completing a data-word transfer.
SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data-word. An interrupt
is generated after a data buffer transfer.
When configured in host mode, the ADSST-2185KST-133 has
a 16-bit Internal DMA port (IDMA port) for connection to
•
external systems. The IDMA port is made up of 16 data/address
pins and five control pins. The IDMA port provides transparent,
direct access to the DSP’s on-chip program and data RAM.
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ADSST-EM-3035
•
SPORT0 has a multichannel interface to selectively receive and
transmit a 24- or 32-word, time-division multiplexed, serial
bitstream.
Pin Descriptions
•
SPORT1 can be configured to have two external interrupts
(IRQ0 and
IRQ1)
and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
The ADSST-2185KST-133 is available in a 100-lead TQFP
package. To maintain maximum functionality and reduce pack-
age size and pin count, some serial ports, programmable flags,
interrupt and external bus pins have dual, multiplexed function-
ality. The external bus pins are configured during RESET only,
while serial port pins are software configurable during program
execution. Flag and interrupt functionality is retained concur-
rently on multiplexed pins. In cases where pin functionality is
reconfigurable, the default state is shown in plain text; alternate
functionality is shown in italics.
Table I. Common-Mode Pins
Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2+PF7
IRQL0+PF5
IRQL1+PF6
IRQE+PF4
Number Input/
of Pins Output Function
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin
Name(s)
Number Input/
of Pins Output Function
I
I
O
I/O
I/O
Mode Select Input-Checked
only During RESET
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive
Interrupts
Flag In, Flag Out
2
Power-Down Control Input
Power-Down Control Output
Output Flags
VDD and GND
I
I
O
O
O
O
O
O
O
O
O
I
I
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory
Select Output
Memory Read Enable Output
Memory Read Enable Output
Edge- or Level-Sensitive
Interrupt Request
1
Level-Sensitive
Interrupt Requests
1
PF0 (Mode A) 1
CLKIN,
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1:0
F1, F0
PWD
PWDACK
FL0, FL1,
FL2
VDD
AND
GND
EX-Port
2
1
5
5
1
1
3
16
I
O
O
I
1
1
I
I
I/O
I
PF3
1
PF2 (Mode C) 1
PF1 (Mode B) 1
I
Level-Sensitive
Interrupt
Requests
1
Edge-Sensitive
Interrupt Requests
1
Programmable I/O Pin
Programmable I/O Pin Mode
Select Input-Checked only
During RESET
Mode Select Input-Checked
only During RESET
9
I/O
For Emulation Use
NOTES
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable
the corresponding interrupts, the DSP will vector to the appropriate interrupt
vector address when the pin is asserted, either by external devices or set as a
programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software
configurable.
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ADSST-EM-3035
100-Lead TQFP Package Pinout
93 PF1 [MODE B]
89 PF2 [MODE C]
94 PF0 [MODE A]
100 A3/IAD2
99 A2/IAD1
96 PWDACK
98 A1/IAD0
91
PWD
92 GND
80 GND
79 D19
95
BGH
90 VDD
88 PF3
84 D23
83 D22
78 D18
77 D17
A4/IAD3
A5/IAD4
GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
1
2
3
4
5
6
7
8
9
PIN 1
IDENTIFIER
76 D16
81 D20
82 D21
86 FL1
85 FL2
87 FL0
97 A0
75 D15
74 D14
73 D13
72 D12
71 GND
70 D11
69 D10
68 D9
67 VDD
66 GND
65 D8
64 D7/IWR
63 D6/IRD
62 D5/IAL
61 D4/IS
60 GND
59 VDD
58 D3/IACK
57 D2/IAD15
56 D1/IAD14
55 D0/IAD13
54
BG
53
EBG
52
BR
51
EBR
IRQL0+PF5
27
GND 28
IRQL1+PF6
29
IRQ2+PF7
30
DT0 31
TFS0 32
RFS0 33
DR0 34
SCLK0 35
VDD 36
DT1/FO 37
TFS1/IRQ1 38
RFS1/IRQ0 39
DR1/FI 40
GND 41
SCLK1 42
ERESET
43
RESET
44
EMS
45
EE 46
ECLK 47
ELOUT 48
ELIN 49
IRQE+PF4
26
EINT
50
A12/IAD11 10
A13/IAD12 11
GND 12
CLKIN 13
XTAL 14
VDD 15
CLKOUT 16
GND 17
VDD 18
WR
19
RD
20
BMS
21
DMS
22
PMS
23
IOMS
24
CMS
25
ADSST-2185KST-133
TOP VIEW
(Not to Scale)
REV. 0
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