ZL50064 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > ZL50064

Preview

ZL50064: Description16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs; File Size530KB，68 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

Download Datasheet Compare View All

ZL50064 Overview

16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs

Preview

Download Datasheet

View All

ZL50062/4

16K-Channel Digital Switch with High Jitter

Tolerance, Single Rate (2, 4, 8,

or 16Mbps), and 64 Inputs and 64 Outputs

Data Sheet

Features

•

16,384-channel x 16,384-channel non-blocking

unidirectional switching.The Backplane and Local

inputs and outputs can be combined to form a

non-blocking switching matrix with 64 input

streams and 64 output streams

8,192-channel x 8,192-channel non-blocking

Backplane input to Local output stream switch

8,192-channel x 8,192-channel non-blocking

Local input to Backplane output stream switch

8,192-channel x 8,192-channel non-blocking

Backplane input to Backplane output switch

8,192-channel x 8,192-channel non-blocking

Local input to Local output stream switch

Backplane port accepts 32 input and 32 output

ST-BUS streams with fixed data rates of

2.048Mbps, 4.096Mbps, 8.192Mbps or

16.384Mbps

Local port accepts 32 input and 32 output ST-

BUS streams with fixed data rates of 2.048Mbps,

4.096Mbps, 8.192Mbps or 16.384Mbps

Exceptional input clock jitter tolerance (17ns)

•

Ordering Information

ZL50062GAC

ZL50064QCC

256-Ball PBGA

256-Pin LQFP

November 2003

•

-40°C to +85°C

Per-stream bit delay for Local and Backplane

input streams

Per-stream advancement for Local and Backplane

output streams

Constant 2-frame throughput delay for frame

integrity

Per-channel high impedance output control for

Local and Backplane streams

Per-channel driven-high output control for Local

and Backplane streams

Per-channel message mode for Local and

Backplane output streams

Connection memory block programming for fast

device initialization

•

DD_IO

DD_CORE

SS (GND)

RESET

ODE

BSTi0-31

Backplane Data Memories

(8,192 channels)

Local

Interface

LSTi0-31

Backplane

Interface

BSTo0-31

Backplane

Connection Memory

(8,192 locations)

Local

Connection Memory

(8,192 locations)

Local

Interface

LSTo0-31

BORS

Local Data Memories

(8,192 channels)

LORS

FP8i

Input

Timing Unit

Output

Timing

Unit

FP8o

FP16o

C8o

C16o

C8i

PLL

Microprocessor Interface

and Internal Registers

Test Port

DD_PLL

DS CS R/W

A14-0

DTA

D15-0

TMS TDi TDo TCK TRST

Figure 1 - ZL50062/4 Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL50062/4

Device Overview

Data Sheet

The ZL50062 and ZL50064 are two different packages of the same device. They have the same functionality

except that ZL50064 does not have 16.384MHz output clock and frame pulse (C16o and FP16o) due to package

differences. The ZL50062/4 has two data ports, the Backplane and the Local port. The device can operate at four

different data rates, 2.048Mbps, 4.096Mbps, 8.192Mbps or 16.384Mbps. All 64 input and 64 output streams must

operate at the same data rate.

The ZL50062/4 contains two data memory blocks (Backplane and Local) to provide the following switching path

configurations:

•

Input-to-Output Unidirectional, supporting 16K x 16K switching

Backplane-to-Local Bi-directional, supporting 8K x 8K data switching,

Local-to-Backplane Bi-directional, supporting 8K x 8K data switching,

Backplane-to-Backplane Bi-directional, supporting 8K x 8K data switching.

Local-to-Local Bi-directional, supporting 8K x 8K data switching.

The device contains two connection memory blocks, one for the Backplane output and one for the Local output.

Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly

from the connection memory contents (Message Mode).

In Connection Mode, the contents of the connection memory define, for each output stream and channel, the

source stream and channel (stored in data memory) to be switched.

In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output

streams on a per channel basis. This feature is useful for transferring control and status information to external

circuits or other ST-BUS devices.

The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing

for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI-

Bus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the

establishment of full switch functionality. During this period, the input frame pulse format is determined before

switching begins.

The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of

the Backplane and Local ports.

A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and

switching configurations. The microprocessor port provides access for Register read/write, Connection Memory

read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control

signals. The microprocessor may monitor channel data in the Backplane and Local data memories.

The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.

The ZL50062 and ZL50064 are each available in one package:

•

ZL50062: a 17mm x 17mm body, 1mm ball-pitch, 256-PBGA.

ZL50064: a 28mm x 28mm body, 0.40mm pin-pitch, 256-LQFP.

Zarlink Semiconductor Inc.

ZL50062/4

Table of Contents

Data Sheet

1.0 Unidirectional and Bi-directional Switching Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.1 Flexible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration) . . . . . . . . . . . . . . . . . . 18

1.1.2 Non-Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.1.3 Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.1 Unidirectional Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.2 Backplane-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.3 Local-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.4 Backplane-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.5 Local-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.6 Port Data Rate Modes and Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.6.1 Local Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.6.2 Backplane Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2 Frame Pulse Input and Master Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3 Input Frame Pulse and Generated Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.5 Input Clock Jitter Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.0 Input and Output Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1 Input Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1.1 Input Bit Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2 Output Advancement Programming (Backplane and Local Output Streams) . . . . . . . . . . . . . . . . . . . . . . 25

4.0 Port high impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.0 Device Power-up, Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.0 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1 Local Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.2 Backplane Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.3.1 Memory Block Programming Procedure: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.2.2.3 The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

12.0 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

13.0 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Zarlink Semiconductor Inc.

ZL50062/4

Table of Contents

Data Sheet

13.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

13.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

13.3 Local Input Bit Delay Registers (LIDR0 to LIDR31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

13.3.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

13.5 Local Output Advancement Registers (LOAR0 to LOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

13.6 Backplane Output Advancement Registers (BOAR0 - BOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13.8 Bit Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13.9 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Zarlink Semiconductor Inc.

ZL50064 Related Products

	ZL50064	ZL50062	ZL50062GAC
Description	16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs	16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs	16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs

Recommended Resources

Current sensor interface circuit diagram

Positive and negative 10V reference voltage circuit

5V-10A regulated power supply circuit diagram composed of 5G14

4 types of TTL crystal oscillator circuit diagrams

Ring counting circuit

Computer motherboard circuit diagram 820 1_29

Multisim Circuit System Design and Simulation Tutorial: "Multisim Circuit System Design and Simulation Tutorial" combines a large number of examples to introduce the basic operations, advanced functions, component libraries, various instruments, and circui...; arui1999 Download Centre

[NXP Rapid IoT Review] Reduce the CPU frequency (K64) to save power: [i=s]This post was last edited by cruelfox on 2019-1-19 17:42[/i] This Rapid-IoT kit is really a power hog, and the main power consumer is the K64 MCU, because I found that the project downloaded from...; cruelfox RF/Wirelessly

[GD32L233C-START Review] 13. CAU encryption algorithm DES/TDES: For previous posts, please refer to:【GD32L233C-START Review】1. Unboxing [GD32L233C-START Review] 2. Create a new project step by step [GD32L233C-START Evaluation] 3. Porting FreeRTOS to GD32L233 【GD32...; hehung GD32 MCU

Wireless Sensor Network Overview: 1. History of wireless sensor network developmentThe first stage: the earliest can be traced back to the Vietnam War when traditional sensor systems were used The second stage: between the 1980s and 1...; Jacktang Wireless Connectivity

[Silicon Labs BG22-EK4108A Bluetooth Development Evaluation] 3. Lighting Experiment: [i=s]This post was last edited by webber310 on 2022-1-7 19:58[/i]3. Lighting Experiment In the previous article, we introduced the hardware of BG22-EK4108A and the installation of the development envi...; webber310 Development Kits Review Area

CC1310 Two-wire Serial Bootloader Solution: CC1310 is a Sub-1G-capable SOC in TI Simplelink MCU series. In response to the application requirements of many customers who need to upgrade firmware via serial port, CC1310 has a built-in ROM-based ...; Jacktang RF/Wirelessly

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components