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System ACE™ MPM Solution
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DS087 (v1.2) June 7, 2002
Advance Product Specification
Summary
•
System level, high capacity, pre-configured solution for
Virtex™ Series FPGAs, Virtex-II Series Platform
FPGAs, and Spartan™ FPGAs
Industry standard Flash memory die combined with
Xilinx controller technology in a single package
Effortless density migration:
- XCCACEM16-BG388I (16 Megabit (Mb))
- XCCACEM32-BG388I (32 Mb)
- XCCACEM64-BG388I (64 Mb)
All densities are available in the 388-pin Ball Grid Array
package
VCC I/O: 1.8V, 2.5V, and 3.3V
Configuration rates up to 152 Mb per second (Mb/s)
Flexible configuration solution:
- SelectMAP (control up to four FPGAs)
- Slave-Serial
- Concurrent Slave-Serial (up to eight separate
chains)
•
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Patented compression technology (up to 2x
compression)
JTAG interface allows:
- Access to the standard Flash memory
- Boundary Scan testing
Native interface to the standard Flash memory is
provided for:
- External parallel programming
- Processor access to unused Flash memory
locations
Supports up to eight separate design sets (selectable
by mode pins or via JTAG), enabling systems to
reconfigure FPGAs for different functions
Compatible with IEEE Standard 1532
User-friendly software to format and program the
bitstreams into the standard Flash via the patented
Flash programming engine
Internet Reconfigurable Logic (IRL) upgradeable
system
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Description
The System ACE Multi-Package Module (MPM) solution
addresses the need for a space-efficient, pre-engineered,
high-density configuration solution in multiple FPGA sys-
tems. The System ACE technology is a ground-breaking
in-system programmable configuration solution that pro-
vides substantial savings in development effort and cost per
bit over traditional PROM and embedded solutions for high
capacity FPGA systems. As shown in
Figure 1,
the System
ACE MPM solution is a multi-package module that includes
the System ACE MPM controller, a configuration PROM,
and an AMD Flash Memory.
The System ACE MPM has four major interfaces. (See
Figure 2.)
The boundary scan JTAG interface is provided for
boundary scan test and boundary-scan-based Flash mem-
ory programming. The system control interface provides an
input for the system clock, design set selection pins, system
configuration control signals, and system configuration sta-
tus signals.
The native Flash memory interface provides direct read and
write access to the Flash memory unit. The target FPGA
interface provides the signals to configure target FPGAs via
the Slave-Serial, concurrent Slave-Serial, or SelectMAP
configuration modes.
Separate power pins provide voltage compatibility control
for the target FPGA configuration interface and for the sys-
tem control/status interface.
See
Figure 3
for a complete view of the components and
schematic of the signals in the System ACE MPM.
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS087 (v1.2) June 7, 2002
Advance Product Specification
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1-800-255-7778
1
System ACE™ MPM Solution
R
16/32/64 Mbit AMD Flash Memory
Metal Lid
Package: 48 pin TSOP
Dimensions: 20 x 12 x 1.2 mm
PROM XC18V01
Package: VQ44
Dimensions: 12 x 12 x 1.2 mm
MPM BGA Module
Virtex XCV50E Configuration Controller
Package: CS144
Dimensions: 12 x 12 x 1.2 mm
System ACE MPM BG388
Complete Assembly
Dimensions: 35 x 35 x 2.7 mm
DS087_01_081501
Figure 1:
System ACE MPM Assembly
System ACE MPM
Boundary
Scan
Interface
System
Control
Interface
XCV50E
Configuration
Controller
PROM
Slave-Serial
or SelectMAP
Target
FPGA
Interface
Native
Flash
Memory
AMD
Flash
Memory
ds087_02_091001
Figure 2:
System ACE MPM Interfaces
2
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DS087 (v1.2) June 7, 2002
Advance Product Specification
R
System ACE™ MPM Solution
System ACE MPM
TDI
TCK
TMS
TDO
RESET * 6
4.7k
3.3v
XCV50E
4.7k
3.3v
XC18V01
TCK
TMS
TDO
CLK
D0
OE/Reset
CE
CF
DEVRDY
FCMRESET
SYSRESET
SYSCLK
BITSTRSEL[0-2]
STATUS[0-3]
CFG_MODE[0-2]
CFG_CLK
CFG_BUSY
CFG_INIT
CFG_DONE
CFG_PROG
CFG_WRITE
CFG_CS[0-3]
CFG_DATA[0-7]
TDI
AMD Flash
GND
RESET
FLASH_IO_LEVEL*
2
V
IO
/BYTE *
2
A0-A21 *
1
DQ0-DQ15
OE
CE
WE
ACC/WP *
5
ACC *
4
ACC *
4
RY/BY *
3
TCK
TMS
TDO
RESET
A0-A21 *
1
DQ0-DQ15
OE
CE
WE
WP *
5
RY/BY *
3
FCM_ENABLE
SYSRESET
CCLK
DIN
INIT
DONE
PROGRAM
TDI
300
A0-A21 *
1
DQ0-DQ15
OE
CE
WE
WP *
5
RY/BY *
3
FCM_ENABLE
FLASH_VCCO
CFG_VCCO
CTRL_VCCO
VCCO
6,7
VCCO
0,1
SYSCLK
BITSTRSEL[0-2]
STATUS[0-3]
CFG_MODE[0-2]
CFG_CLK
CFG_BUSY
CFG_INIT
CFG_DONE
VCCO
2,3,4,5
CFG_PROG
CFG_WRITE
CFG_CS[0-3]
CFG_DATA[0-7]
*1 A21 for XCCACEM64 only; A20 for XCCACEM32 and XCCACEM64 only.
*2 V for XCCACEM64; BYTE for XCCACEM16 and XCCACE32.
IO
*3 XCCACEM16 and XCCACEM32 only.
*4 XCCACEM64 only.
*5 WP on XCCACEM64; ACC/WP on XCCACEM32. Do not apply V
HH
to ACC/WP.
*6 Do not apply V to RESET.
ID
DS087_03_091701
Figure 3:
System ACE MPM schematic
DS087 (v1.2) June 7, 2002
Advance Product Specification
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System ACE™ MPM Solution
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Pin Descriptions
This section provides native Flash interface, Boundary
Scan, and target FPGA configuration pinout information.
with a few restrictions. See Note 1 and
Table 1
for descrip-
tions of the restrictions.
Notes:
1. All of the native Flash memory interface pins are connected to
the System ACE MPM controller (except where explicitly
noted in the pin description). The FCM_ENABLE pin must be
held Low to externally access the Flash memory without
contention with the System ACE MPM controller.
Native Flash Interface Pins
All of the native Flash memory pins are routed to pins on the
System ACE MPM ball-grid-array. Thus, the Flash memory
is available to the system for direct read and write access
Table 1:
Native Flash Memory Interface Pins
Pin Name
A0-A21
DQ0-DQ15
RESET
Pin Type
I/O
I/O
I/O
Description
Flash memory address bus. A21 exists on the XCCACEM64 only. A20 exists
on the XCCACEM32 and XCCACEM64 only.
Flash memory data bus. DQ15 becomes the A-1 pin in the XCCACEM16 and
XCCACEM32 when the BYTE mode is active.
Flash memory hardware reset. When asserted, all Flash operations are
immediately terminated and Flash is reset to read mode. When RESET and CE
are held High, the Flash memory is put into standby mode. Do not apply V
ID
to
the RESET pin. The RESET is connected to the System ACE MPM controller
that has a maximum tolerance of 3.6 V.
Flash memory chip enable. When RESET and CE are held High, the Flash
memory is put into standby mode.
Flash memory output enable.
Flash memory write enable.
Flash memory ready/busy signal. Open-drain output. When Low, the RD/BY
signal indicates that the Flash is actively erasing, programming, or resetting.
XCCACEM16 and XCCACEM32 only.
Flash memory hardware write protect.
Flash memory accelerated mode pin. Do not apply V
HH
to the XCCACEM32
WP/ACC pin. The XCCACEM32 WP/ACC pin is connected to the System ACE
MPM controller that has a maximum tolerance of 3.6 V. The XCCACEM64 ACC
pin is independent of the rest of the System ACE MPM and may be used to put
the Flash memory into accelerated program operation.
Flash memory V
IO
pin on the XCCACEM64 only. This pin must be connected
to 3.3V for compatibility with the System ACE MPM controller.
Flash memory byte-wide data bus mode. XCCACEM16 and XCCACEM32
only. This pin must be connected to 3.3V for compatibility with the System ACE
MPM controller and thus only the 16-bit, word mode is available for accessing
the Flash memory in the system.
CE
OE
WE
RY/BY
I/O
I/O
I/O
Output
WP
ACC
I/O
Input
FLASH_IO_LEVEL
BYTE
Input
Input
Boundary Scan Pins
The System ACE MPM controller (Virtex-E XCV50E) and
the System ACE MPM controller PROM (XC18V01) are
both IEEE Standard 1149.1 compatible devices. The Sys-
tem ACE MPM connects these devices into an internal scan
chain comprised of the XC18V01 device followed by the
XCV50E device. The internal scan chain is accessible
through the boundary scan test access port (TAP) on the
BG388 package. See
Table 2.
4
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1-800-255-7778
DS087 (v1.2) June 7, 2002
Advance Product Specification
R
System ACE™ MPM Solution
Table 2:
IEEE 1149.1 Boundary Scan Pins
Pin Name
TCK
Pin Type
Input
Description
IEEE 1149.1 test clock pin. The System ACE MPM TCK pin is connected to the
XCV50E and XC18V01 TCK pins. By default, the XCV50E has an internal
pull-up resistor on its TCK pin.
IEEE 1149.1 test mode select pin. The System ACE MPM TMS pin is
connected to the XCV50E and XC18V01 TMS pins which have internal pull-up
resistors.
IEEE 1149.1 test data input pin. The System ACE MPM TDI is connected to
the XC18V01 TDI pin which has an internal pull-up resistor.
IEEE 1149.1 test data output pin. The System ACE MPM TDO pin is connected
to the XCV50E TDO pin which by default has an internal pull-up resistor.
TMS
Input
TDI
TDO
Input
Output
Target FPGA Configuration Pins
Table 3
provides target FPGA configuration pins.
Table 3:
Target FPGA Configuration Pins
Pin Name
CFG_DATA[0]
Pin Type
Output
Description
For Slave-Serial configuration mode, CFG_DATA[0] is the serial data signal for
Serial-Slave Chain 0 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 0. For Slave-SelectMAP configuration mode, CFG_DATA[0]
is the data bit 0 on the SelectMAP bus and is connected to D0 on all target
FPGAs.
For Slave-Serial configuration mode, CFG_DATA[1] is the serial data signal for
Serial-Slave Chain 1 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 1. For Slave-SelectMAP configuration mode, CFG_DATA[1]
is the data bit 1 on the SelectMAP bus and is connected to D1 on all target
FPGAs.
For Slave-Serial configuration mode, CFG_DATA[2] is the serial data signal for
Serial-Slave Chain 2 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 2. For Slave-SelectMAP configuration mode, CFG_DATA[2]
is the data bit 2 on the SelectMAP bus and is connected to D2 on all target
FPGAs.
For Slave-Serial configuration mode, CFG_DATA[3] is the serial data signal for
Serial-Slave Chain 3 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 3. For Slave-SelectMAP configuration mode, CFG_DATA[3]
is the data bit 3 on the SelectMAP bus and is connected to D3 on all target
FPGAs.
For Slave-Serial configuration mode, CFG_DATA[4] is the serial data signal for
Serial-Slave Chain 4 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 4. For Slave-SelectMAP configuration mode, CFG_DATA[4]
is the data bit 4 on the SelectMAP bus and is connected to D4 on all target
FPGAs.
For Slave-Serial configuration mode, CFG_DATA[5] is the serial data signal for
Serial-Slave Chain 5 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 5. For Slave-SelectMAP configuration mode, CFG_DATA[5]
is the data bit 5 on the SelectMAP bus and is connected to D5 on all target
FPGAs.
CFG_DATA[1]
Output
CFG_DATA[2]
Output
CFG_DATA[3]
Output
CFG_DATA[4]
Output
CFG_DATA[5]
Output
DS087 (v1.2) June 7, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
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