AT40K05-2DQC datasheet, PDF - EEWORLD Datasheet

AT40K05-2DQC: DescriptionFPGA - Field Programmable Gate Array 5K - 10K GATE 5V LOW POWER - 2NS; CategoryProgrammable logic devices Programmable logic; File Size60KB，5 Pages; ManufacturerAtmel (Microchip)

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FPGA - Field Programmable Gate Array 5K - 10K GATE 5V LOW POWER - 2NS

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	QFP
package instruction	FQFP, QFP208,1.2SQ,20
Contacts	208
Reach Compliance Code	compliant
Other features	MAXIMUM USABLE GATES 10000
Combined latency of CLB-Max	2.2 ns
JESD-30 code	S-PQFP-G208
JESD-609 code	e0
length	28 mm
Humidity sensitivity level	3
Configurable number of logic blocks	256
Equivalent number of gates	5000
Number of entries	128
Number of logical units	256
Output times	128
Number of terminals	208
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256 CLBS, 5000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP208,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	28 mm

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