DATASHEET
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
Recommended Applications
One output synthesizer for PCIe Gen1/2
IDT5V41064
Features/Benefits
•
16-pin QFN package; very small board footprint
•
Spread-spectrum capable; reduces EMI
•
Outputs can be terminated to LVDS; can drive a wider
variety of devices
General Description
The IDT5V41064 is a PCIe Gen2 compliant spread
spectrum capable clock generator. The device has 1
differential HCSL output and can be used in communication
or embedded systems to substantially reduce
electro-magnetic interference (EMI). Spread spectrum can
be enabled via a select pin.
•
Spread enable via pin selection; no software required to
configure device
•
Industrial temperature range available; supports
demanding embedded applications
•
For PCIe Gen3 applications, see the 5V41234
Output Features
•
1 - 0.7V current mode differential HCSL output pairs
Key Specifications
•
Cycle-to-cycle jitter < 100 ps
•
PCIe Gen2 phase jitter < 3.0ps RMS
Block Diagram
VDD
SS1
Control
Logic
Phase Lock
Loop
CLK
CLK
X1
25 MHz
crystal /clock
X2
Clock
Buffer/
Crystal
Oscillator
Crystal Tuning Capacitors
GND
R
R
(IREF)
IDT®
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
1
IDT5V41064
APRIL 17, 2017
IDT5V41064
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
Pin Assignment
VDD
NC
NC
NC
Spread Spectrum Select Table
SS1
0
1
Spread%
-0.5% down
No spread
GND
X1
X2
NC
1
13
CLK
CLK
GND
VDDA
5
9
SS1
IREF
16-pin QFN
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
X1
X2
NC
GND
SS1
IREF
NC
VDDA
GND
CLK
CLK
NC
NC
VDD
NC
GND
Power
XI
XO
–
Power
Input
Output
–
Power
Power
Output
Output
–
–
Power
–
NC
Connect to ground.
Crystal or clock input. Connect to 25 MHz crystal or single-ended clock.
Crystal connection. Connect to parallel mode crystal. Leave floating if X1 is driven by
single-ended clock.
No connect.
Connect to ground.
Spread Select 1. See table above. Internal pull-up resistor.
475 precision resistor must be attached to this pin, which is connected to internal
current source.
No connect.
Connect to 3.3V and filter as analog supply.
Connect to ground.
HCSL complementary output clock.
HCSL true output clock.
No connect.
No connect.
Connect to 3.3 V for OSC and digital circuits.
No connect.
IDT®
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
2
IDT5V41064
APRIL 17, 2017
IDT5V41064
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
Applications Information
External Components
A minimum number of external components are required for
proper operation.
Output Structures
IREF
=2.3 mA
6*IREF
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected
between VDD and the ground plane (pin 4) as close to the
VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into IDT pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal with
C
L
= 16 pF should be used. This crystal must have less than
300 ppm of error across temperature in order for the
IDT5V41064 to meet PCI Express specifications.
R
R
475
See Layout
Guidelines
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
C
L
= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50, then R
R
= 475
(1%), providing IREF of 2.32 mA. The output current (I
OH
) is
equal to 6*IREF.
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41064.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41064 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the
PCI-Express Layout Guidelines
section.
The IDT5V41064 can also be terminated to LVDS
compatible voltage levels. See Layout Guidelines section.
IDT®
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
3
IDT5V41064
APRIL 17, 2017
IDT5V41064
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
Layout Guidelines for PCI Express
PCIe Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, route as non-coupled 50ohm trace
0.5 max
L2 length, route as non-coupled 50ohm trace
0.2 max
L3 length, route as non-coupled 50ohm trace
0.2 max
Rs
33
Rt
49.9
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
2 min to 16 max
1.8 min to 14.4 max
inch
inch
1
1
0.25 to 14 max
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L1
Rs
L2
L4
L4'
L1'
Rs
HCSL Output Buffer
L2'
Rt
Rt
PCI Express
Down Device
REF_CLK Input
L3'
L3
Figure 2: PCI Express Connector Routing
L1
Rs
L2
L4
L4'
L1'
Rs
HCSL Output Buffer
L2'
Rt
Rt
PCI Express
Add-in Board
REF_CLK Input
L3'
L3
IDT®
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
4
IDT5V41064
APRIL 17, 2017
IDT5V41064
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
Layout Guidelines for LVDS and Other Applications
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
Vp-p
Vcm
R1
R2
R3
R4
Note
0.45v
0.22v
1.08
33
150
100
100
0.58
0.28
0.6
33
78.7
137
100
0.80
0.40
0.6
33
78.7
none
100
ICS874003i-02 input compatible
0.60
0.3
1.2
33
174
140
100
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L1
R1a
L2
R3
L4
L4'
R4
L1'
R1b
HCSL Output Buffer
L2'
R2a
R2b
Down Device
REF_CLK Input
L3'
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
8.2K 5%
R6a, R6b
1K 5%
Cc
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
Cc
L4
L4'
Cc
R6a
R5b
R6b
PCIe Device
REF_CLK Input
IDT®
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
5
IDT5V41064
APRIL 17, 2017
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