GNDO
VCCO
Qb2
Qb3
GNDO
GNDO
Qc0
Qc1
VCCO
24 23 22 21 20 19 18 17
16
25
15
26
27
28
29
30
31
32 1
2 3 4
5
6 7 8
14
GNDO
VCCO
VCCO
Qb1
Qb0
Qa4
Qa3
VCO_Sel
fselc
fselb
fsela
MR/OE
REFCLK
GNDI
FBin
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
1
2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2952
Low Voltage PLL Clock Driver
Features
• ±100ps Cycle-to-Cycle Jitter
• Fully Integrated PLL
• Output Frequency up to 180MHz
• High-Impedance Disabled Outputs
• Compatible with PowerPC, Intel, and High-Performance
RISC Microprocessors
• Configurable Output Frequency
• 32-Pin LQFP Package (FB)
Description
The PI6C2952 is a 3.3V compatible, PLL-based clock driver device
targeted for high-performance clock applications. The device fea-
tures a fully integrated PLL with no external components
required. With output frequencies up to 180MHz and eleven low-
skew outputs, the PI6C2952 is well suited for high-performance
designs. The device employs a fully differential PLL design to
optimize jitter and noise rejection performance.
The PI6C2952 features three banks of individually configurable
outputs. The banks contain 5 outputs, 4 outputs, and 2 outputs. The
internal divide circuitry allows for output frequency ratios of 1:1, 2:1,
3:1, and 3:2:1. The output frequency relationship is controlled by the
fsel frequency control pins. The fsel pins and other inputs are
LVCMOS/LVTTL compatible inputs.
The PI6C2952 uses external feedback to the PLL. This features
allows the device to be used as a “zero delay” buffer. Any of the
eleven outputs can be used as feedback to the PLL. To optimize PLL
stability and jitter performance,the VCO_Sel pin allows for the
choice of two VCO ranges. For board level test, the MR/OE pin
allows a user to force the outputs into high impedance. For system
debug, the PI6C2952’s PLL can be bypassed. When forced to a logic
HIGH, the PL_LEN input routes the signal on the RefClk input
around the PLL directly to the internal dividers. Because the signal
is routed through the dividers, it may take several transitions of the
RefClk to affect a transition on the outputs. This features allows a
designer to single step the design for debug purposes.
The PI6C2952’s outputs are LVCMOS which are optimally designed
to drive terminated transmission lines. For applications using series-
terminated transmission lines, each PI6C2952 output can drive two
lines. This capability provides an effective fanout of 22, more than
enough clocks for most clock tree designs.
Pin Configuration
VCCO
Qa2
Qa1
GNDO
Qa0
VCCI
VCCA
PLL_En
32-Pin
FB
13
12
11
10
9
1
PS8542A
01/30-06
200-480MHz
V
V
V
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2952
Low Voltage PLL Clock Driver
Block Diagram
PLL_En
REFCLK
Phase
Detector
FBIn
LPF
Qa3
VCO_Sel (Int Pull Down)
fsela (Int Pull Down)
Qa4
Qb0
Qb1
Qb2
Qb3
÷2/÷4
fselc
MR/OE
(Int Pull Down)
(Int Pull Down)
Qc0
Qc1
VCO
÷2
÷4/÷6
(Int Pull Down)
Qa0
Qa1
Qa2
÷4/÷2
fselb (Int Pull Down)
"–1" Has ÷2/÷8
"–2" Has ÷4/÷8
Function Tables
fs e la
0
1
Qan
÷4
÷6
fs e lb
0
1
Qbn
÷4
÷2
fs e lc
0
1
Qcn
÷2
÷4
Pin Name
VCCA
VCCO
VCCI
GNDI
GNDO
De s cription
PLL Power Supply
Output Buffer Power Supply
Internal Core Logic Power Supply
Internal Ground
Output Buffer Ground
Control Pin
VCO_Sel
MR/OE
PLL_En
Logic 'O'
fVCO
Output Enable
Enable PLL
Logic '1'
fVCO/2
High Z
Disable PLL
2
PS8542A
01/30-06
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2952
Low Voltage PLL Clock Driver
Absolute Maximum Ratings*
Symbol
V
CC
V
I
I
IN
T
STOR
Supply Voltage
Input Voltage
Input Current
Storage Temperature Range
–4 0
Parame te rs
M in.
–0.3
–0.3
M a x.
4.6
V
V
DD
+ 0.3
± 20
125
mA
°C
Units
*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
DC Characteristics (T
A
= 0°C to 70° C, V
CC
= 3.3V± 5%)
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
C
IN
C
PD
I
CC
I
CCA
Total ICC Static Current
I
OH
= 20mA (Note1.)
I
OL
= 20mA (Note1.)
Note 2.
Conditions
Characte ris tic
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Maximum Quiescent Supply Current
PLL Supply Current
15
2.7
25
160
mA
20
2.4
0.5
±120
4.0
pF
μΑ
M in.
2.0
Typ
M a x.
3.6
0.8
V
Units
Notes:
1. The PI6C2952 outputs can drive series- or parallel-terminated 50 ohms (or 50 ohms to V
CC
/2) transmission lines on the incident
edge (see Applications Info section).
2. Inputs have pull–up, pull–down resistors that affect input current.
PLL Input Reference Characteristics (T
A
= 0°C to 70°C)
Symbol
t
r
, t
f
f
ref
f
refDC
Parame te rs
TCLK Input Rise/Falls
Reference Input Frequency
Reference Input Duty Cycle
Note 3
25
M in.
M a x.
3.0
Note 3
75
Units
ns
MHz
%
Condition
3. Maximum and minimum input reference is limited by the V
CO
lock range and the feedback divider.
3
PS8542A
01/30-06
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2952
Low Voltage PLL Clock Driver
AC Characteristics (T
A
= 0°C to 70°C, V
CC
= 3.3V± 5%)
Symbol
t
r
, t
f
I
PW
Characte ris tics
Output Rise/Fall Time (Note 4.)
Output Pulse Width (Note 4.)
Output- to- Output Skew Excluding Qa0 (Note 4.)
All Outputs
All Outputs
PLL VCO Lock Range Feedback = VCO/4
Feedback = VCO/6
Feedback = VCO/8
Feedback = VCO/12
Maximum Output Frequency
Qc,Qb (÷2)
Qa,Qb,Qc (÷4)
Qa (÷6)
REFCLK to FB
IN
Delay
Same Frequencies
Same Frequencies
Different Frequencies
VCO_Sel = 0
VCO_Sel = 0
VCO_Sel = 1
VCO_Sel = 1
200
200
200
200
180
120
80
–2 0 0
2
2
±100
Note 5.
10
TBD
0
200
8
ns
10
ps
ms
ps
ps
Conditions
0.8 to 2.0V
M in.
0 . 10
t
CYCLE
/2
–750
t
CYCLE
/2
± 500
Typ.
M ax.
1.0
t
CYCLE
/2
+750
350
450
550
480
480
480
480
MHz
f
max
(Note 4.)
ps
Units
ns
t
OS
f
VCO
t
pd
Notes 4 and 5.
50ohms to V
CC
/2
50ohms to V
CC
/2
t
PLZ
, t
PHZ
Output Disable Time
t
PZL
, t
PZH
Output Enable Time
tjitter
t
lock
t
JP
Cycle–to–Cycle Jitter (Peak–to–Peak)
Maximum PLL Lock Time
Long term Period Jitter
4. 50 ohms to V
CC
/2.
5. t
pd
is specified for 50 MHz input ref, the window will shrink/grow proportionally from the minimum limit with shorter/longer input
reference periods. The t
pd
does not include jitter.
Applications Information
Driving Transmission Lines
The PI6C2952 clock driver was designed to drive high-speed
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user, the output drivers were
designed to exhibit the lowest impedance possible. With an output
impedance of less than 10 ohms, the drivers can drive either
parallel- or series-terminated transmission lines.
PI6C2952
Output
Buffer
R
S
= 43 ohms Z
O
= 50 ohms
IN
7 ohms
OutA
PI6C2952
Output
Buffer
IN
7 ohms
R
S
= 43 ohms
Z
O
= 50 ohms
OutB0
R
S
= 43 ohms Z
O
= 50 ohms
OutB1
Figure 3. Single versus Dual Transmission Lines
4
PS8542A
01/30-06
VOLTAGE (V)
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2952
Low Voltage PLL Clock Driver
In most high performance clock networks point–to–point distribu-
tion of signals is the method of choice. In a point–to–point scheme
either series terminated or parallel terminated transmission lines can
be used. The parallel technique terminates the signal at the end of
the line with a 50ohm resistance to V
CC
/2. This technique draws a
fairly high level of DC current and thus only a single terminated line
can be driven by each output of the PI6C2952 clock driver. For the
series terminated case however there is no DC current draw, thus the
outputs can drive multiple series terminated lines. Figure 3 illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the fanout of
the PI6C2952 clock driver is effectively doubled due to its capability
to drive multiple lines.
The waveform plots of Figure 4 show the simulation results of an
output driving a single line vs two lines. In both cases the drive
capability of the PI6C2952 output buffers is more than sufficient to
drive 50-ohm transmission lines on the incident edge. Note from the
delay measurements in the simulations a delta of only 43ps exists
between the two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain the tight
output–to–output skew of the PI6C2952. The output waveform in
Figure 4 shows a step in the waveform, this step is caused by the
impedance mismatch seen looking into the driver. The parallel
combination of the 43ohm series resistor plus the output impedance
does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
VL = VS (Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.8V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in this
case 4.0ns).
trip delay (In this example: 4.0ns)
3.0
Since this step is well above the threshold region it will not cause any
false clock triggering, however designers may be uncomfortable with
unwanted reflections on the line. To better match the impedances
when driving multiple lines the situation in Figure 5 should be used.
In this case the series terminating resistors are reduced such that
when the parallel combination is added to the output buffer imped-
ance the line impedance is perfectly matched.
PI6C2952
Output
Buffer
7ohms
RS = 36 ohms
RS = 36 ohms
ZO = 50 ohms
ZO = 50 ohms
7 ohms + 36 ohms⏐ 36 ohms = 50 ohms
⏐
50 ohms
25 ohms = 25 ohms⏐
Figure 5. Optimized Dual Line Termination
SPICE level output buffer models are available for engineers who
want to simulate their specific interconnect schemes. In addition IV
characteristics are in the process of being generated to support the
other board level simulators in general use.
Power Supply Filtering
The PI6C2952 is a mixed analog/digital product and as such it exhibits
some sensitivities that would not necessarily be seen on a fully
digital product. Analog circuitry is naturally susceptible to random
noise, especially if this noise is seen on the power supply pins. The
PI6C2952 provides separate power supplies for the output buffers
(V
CCO
) and the internal PLL (V
CCA
) of the device. The purpose of this
design technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog phase–locked
loop. In a controlled environment such as an evaluation board this
level of isolation is sufficient. However, in a digital system environ-
ment where it is more difficult to minimize noise on the power supplies
a second level of isolation may be required. The simplest form of
isolation is a power supply filter on the V
CCA
pin for the PI6C2952.
3.3V
2.5
OutA
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
R
S
= 5-15 ohms
1.0
VCCA
0.5
PI6C2952
0.01µF
22µF
0
VCC
2
4
6
8
TIME (ns)
10
12
14
0.01µF
Figure 4. Single versus Dual Waveforms
Figure 6. Power Supply Filter
5
PS8542A
01/30-06
stm32/stm8
京公网安备 11010802033920号
EEWORLD
