FPGA - Field Programmable Gate Array FPGA - Arria V GT 9168 LABS 544 IOs
| Parameter Name | Attribute value |
| Is it lead-free? | Lead free |
| Is it Rohs certified? | conform to |
| Maker | Altera (Intel) |
| Parts packaging code | BGA |
| package instruction | BGA, BGA1152,34X34,40 |
| Contacts | 1152 |
| Reach Compliance Code | compliant |
| maximum clock frequency | 670 MHz |
| JESD-30 code | S-PBGA-B1152 |
| JESD-609 code | e1 |
| length | 35 mm |
| Humidity sensitivity level | 3 |
| Number of entries | 544 |
| Number of logical units | 242000 |
| Output times | 544 |
| Number of terminals | 1152 |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | BGA |
| Encapsulate equivalent code | BGA1152,34X34,40 |
| Package shape | SQUARE |
| Package form | GRID ARRAY |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 1.15,1.2/3.3,2.5 V |
| Programmable logic type | FIELD PROGRAMMABLE GATE ARRAY |
| Certification status | Not Qualified |
| Maximum seat height | 2.7 mm |
| Maximum supply voltage | 1.18 V |
| Minimum supply voltage | 1.12 V |
| Nominal supply voltage | 1.15 V |
| surface mount | YES |
| technology | CMOS |
| Terminal surface | Tin/Silver/Copper (Sn/Ag/Cu) |
| Terminal form | BALL |
| Terminal pitch | 1 mm |
| Terminal location | BOTTOM |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| width | 35 mm |
| Base Number Matches | 1 |
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