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CY25404ZXI006

Description
Clock Generators & Support Products Quad PLL Program Clk Gen Spread Spectrum
Categorysemiconductor    Analog mixed-signal IC   
File Size120KB,13 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

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CY25404ZXI006 Overview

Clock Generators & Support Products Quad PLL Program Clk Gen Spread Spectrum

CY25404ZXI006 Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerCypress Semiconductor
Product CategoryClock Generators & Support Products
RoHSDetails
TypeProgrammable Clock Generators
PackagingTube
NumOfPackaging1
Factory Pack Quantity74
CY25404
Quad PLL Programmable Clock Generator
with Spread Spectrum
Features
Four fully-integrated phase-locked loops (PLLs)
Input frequency range
External crystal: 8 to 48 MHz
External reference: 8 to 166 MHz clock
Wide operating output frequency range
3 to 166 MHz
Programmable spread spectrum with center and down
spread option and lexmark and linear modulation profiles
Selectable V
DD
supply voltage options:
2.5 V, 3.0 V, and 3.3 V
Selectable output clock voltages, independent of V
DD
supply:
1.8 V, 2.5 V, 3.0 V, and 3.3 V
Frequency select feature with option to select eight different
frequencies over nine clock outputs
Output enable, and SS ON/OFF controls
Low jitter, high accuracy outputs
Ability to synthesize nonstandard frequencies with
Fractional-N capability
Up to nine clock outputs with programmable drive strength
Glitch-free outputs while frequency switching
20-pin TSSOP package
Commercial and Industrial temperature ranges
One-time programmability
For programming support, contact
Cypress technical support
or send an email to
clocks@cypress.com
Benefits
Multiple high-performance PLLs allow synthesis of unrelated
frequencies
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
Application specific programmable electromagnetic
interference (EMI) reduction using spread spectrum for
clocks
Programmable PLLs for system frequency margin tests
Meets critical timing requirements in complex system
designs
Suitability for PC, consumer, portable, and networking
applications
Capable of zero parts per million (PPM) frequency synthesis
error
Uninterrupted system operation during clock frequency
switch
Application compatibility in standard and low-power systems
For a complete list of related documentation, click
here.
Block Diagram
XIN/
EXCLKIN
XOUT
OSC
PLL1
Crossbar
Switch
Output
Dividers
and
Bank
2
Bank
1
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Control
Bank
3
FS 0
FS 1
FS 2
MUX
and
Control
Logic
PLL2
Drive
Strength
CLK8
CLK9
PLL3
(SS)
PLL4
(SS)
SSON
OE
Cypress Semiconductor Corporation
Document #: 001-43258 Rev. *G
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 19, 2017
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