262,144-bit Static Random-Access Memory (SRAM) device organized as
32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including Pentium
TM
,
PowerPC
TM
, and port able computing. All iance’s advanced circuit design and process t echniques permit 5.0V op eration
without sacrificing performance or operating margins.
The device enters
standby mode
when CE is high. Equal addres s access and cycle times (t
AA
, t
RC
, t
WC
) of 12 ns with output
enable access times (t
OE
) of 6 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory
expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or ou tput enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C256B is packaged in
high volume industry standard packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
Note:
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.5
–0.5
–
–55
–55
–
Max
+7.0
V
CC
+ 0.5
1.25
+125
+125
50
Unit
V
V
W
o
C
o
C
mA
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress ratin g only and functional
operation of the device at the se or any other conditions outside those indicated in th e operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
Data
High Z
High Z
D
OUT
D
IN
Mode
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (I
CC
)
H
L
L
L
H = V
IH
, L = V
IL
, x = Don’t care.
V
LC
= 0.2V, V
HC
= V
CC
- 0.2V.
Other inputs
≥
V
HC
or V
LC
.
X
H
H
L
X
H
L
X
Notes:
12/5/06; V.1.0
Alliance Memory
P. 2 of 8
AS7C256B
®
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature (Industrial)
Note:
Symbol
V
CC
V
IH
V
IL
(1)
T
A
Min
4.5
2.2
-0.5
(1)
–40
Typical
5.0
–
–
–
Max
5.5
V
CC
+0.5
0.8
85
Unit
V
V
V
o
C
1 V
IL
min = –1.5V for pulse width less than 10ns, once per cycle.
DC operating characteristics (over the operating range)
1
Parameter
Input leakage current
Output leakage current
Operating power supply current
Symbol
|I
LI
|
|I
LO
|
I
CC
I
SB
Standby power supply current
I
SB1
Output voltage
Notes:
V
OL
V
OH
Test conditions
V
CC
= Max,
V
in
= GND to V
CC
V
CC
= Max,
CS
= V
IH
,
V
OUT
= GND to V
CC
V
CC
= Max, CE
≤
V
IL
f = f
Max
, I
OUT
= 0mA
V
CC
= Max, CE
>
V
IH
f = f
Max
, I
OUT
= 0mA
V
CC
= Max, CE
>
V
CC
–0.2V
V
IN
< GND + 0.2V or
V
IN
> V
CC
–0.2V, f = 0
(2)
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
AS7C256B-1
Min
–
–
–
–
–
–
2.4
Max
5
5
150
40
15
0.4
–
Unit
µA
µA
mA
mA
mA
V
V
All values are maximum guaranteed values.
f
Max
= 1/t
RC
, only address inputs cycling at f
Max
, f = 0 means that no inputs are cycling.
Capacitance (f = 1MHz, T
a
= room temperature, V
CC
= NOMINAL)
2
Parameter
Symbol
C
IN
C
I/O
Signals
I/O
Input capacitance
I/O capacitance
Note:
A, CE, WE, OE
Test conditions
V
in
= 3dV
V
out
= 3dV
Max
7
7
Unit
pF
pF
This parameter is guaranteed by device characterization, but is not production tested.
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