56F805
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F805
Rev. 16
09/2007
freescale.com
Document Revision History
Version History
Rev. 16
Description of Change
Added revision history.
Added this text to footnote 2 in
Table 3-8:
“However, the high pulse width does not have to
be any particular percent of the low pulse width.”
56F805 General Description
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Up to 40 MIPS at 80MHz core frequency
DSP and MCU functionality in a unified,
C-efficient architecture
Hardware DO and REP loops
MCU-friendly instruction set supports both DSP
and controller functions: MAC, bit manipulation
unit, 14 addressing modes
31.5K
×
16-bit words (64KB) Program Flash
512
×
16-bit words (1KB) Program RAM
4K
×
16-bit words (8KB) Data Flash
2K
×
16-bit words (4KB) Data RAM
2K
×
16-bit words (4KB) Boot Flash
Up to 64K
×
16-bit words (128KB) each of external
Program and Data memory
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Two 6-channel PWM Modules
Two 4-channel, 12-bit ADCs
Two Quadrature Decoders
CAN 2.0 B Module
Two Serial Communication Interfaces (SCIs)
Serial Peripheral Interface (SPI)
Up to four General Purpose Quad Timers
JTAG/OnCE
TM
port for debugging
14 Dedicated and 18 Shared GPIO lines
144-pin LQFP Package
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6
3
4
6
PWM Outputs
Current Sense Inputs
Fault Inputs
PWM Outputs
Current Sense Inputs
Fault Inputs
A/D1
A/D2
VREF
ADC
PWMA
RSTO
RESET
IRQA
EXTBOOT
IRQB
6
JTAG/
OnCE
Port
VPP
VCAPC V
DD
2
8
V
SS
8*
Digital Reg
Analog Reg
V
DDA
V
SSA
PWMB
Low Voltage
Supervisor
3
4
4
4
4
Quadrature
Decoder 0/
Quad Timer A
Quadrature
Decoder 1/
Quad B Timer
Quad Timer C
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
4
2
4
2
2
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
4096 x 16 Flash
2048 x 16 SRAM
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PAB
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PDB
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IPBB
CONTROLS
16
Quad Timer D
/ Alt Func
CAN 2.0A/B
SCI0
or
GPIO
SCI1
or
GPIO
SPI
or
GPIO
Dedicated
GPIO
XDB2
CGDB
XAB1
XAB2
16-Bit
56800
Core
PLL
CLKO
XTAL
EXTAL
Clock Gen
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INTERRUPT
CONTROLS
16
COP/
Watchdog
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
2
4
14
Applica-
tion-Specific
Memory &
Peripherals
IPBus Bridge
(IPBB)
External
Bus
Interface
Unit
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
A[00:05]
6
10
16
PS Select
DS Select
WR Enable
RD Enable
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
D[00:15]
56F805 Block Diagram
*
includes TCS pin which is reserved for factory use and is tied to VSS
56F805 Technical Data, Rev. 16
Freescale Semiconductor
3
Part 1 Overview
1.1 56F805 Features
1.1.1
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Processing Core
Efficient 16-bit 56800 family processor engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators, including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
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Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
— 31.5K
×
16 bit words of Program Flash
— 512
×
16-bit words of Program RAM
— 4K× 16-bit words of Data Flash
— 2K
×
16-bit words of Data RAM
— 2K
×
16-bit words of Boot Flash
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Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K
×
16 bits of Data memory
— As much as 64K
×
16 bits of Program memory
1.1.3
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Peripheral Circuits for 56F805
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four
Fault inputs, fault tolerant design with dead time insertion; supports both center- and edge-aligned modes
Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions; ADC and
PWM modules can be synchronized
Two Quadrature Decoders each with four inputs or two additional Quad Timers
56F805
Technical Data, Rev. 16
4
Freescale Semiconductor
56F805 Description
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Two General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins
CAN 2.0 B Module with 2-pin port for transmit and receive
Two Serial Communication Interfaces, each with two pins (or four additional GPIO lines)
Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins
Computer Operating Properly (COP) watchdog timer
Two dedicated external interrupt pins
External reset input pin for hardware reset
External reset output pin for system reset
JTAG/On-Chip Emulation (OnCE™) module for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4
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Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
1.2 56F805 Description
The 56F805 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F805 is well-suited for many applications. The 56F805 includes many peripherals
that are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
MCU and DSP applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F805 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F805 also provides two external
dedicated interrupt lines, and up to 32 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F805 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It
also supports program execution from external memory (64K).
56F805 Technical Data, Rev. 16
Freescale Semiconductor
5
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