DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16781
480 OUTPUT TFT-LCD SOURCE DRIVER
DESCRIPTION
The
µ
PD16781 is a source driver for 480-output TFT-LCDs, providing support for only striped pixel array LCD.
The driver consists of a shift register for generating the sampling timing and sample & hold circuits for sampling the
analog voltage. The high picture quality obtained by the alternate sample & hold execution of the two types of on-chip
sample & hold circuits enables employment in applications such as car navigation panels.
FEATURES
• 5.0 V Drive (Dynamic range 4.6 V
P-P
, V
DD2
= 5.0 V)
• 480 Output channel
• f
CLK
= 20 MHz MAX. (V
DD1
= 3.0 V)
• 1-phase/3-phase sampling clocks supported
• Corresponds only to LCD of Stripe array color filter
• Two on-chip sample-and-hold circuits
• Small output deviation between pins (deviation between chip pins:
±20
mV MAX.)
• Switch between right and left shift using the R,/L pin
• Logic power supply voltage (V
DD1
): 3.0 to 5.5 V
• Driver power supply voltage(V
DD2
): 5.0
±
0.5 V
Remark
/xxx indicates active low signal.
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16781N-xxx
Remark
The TCP’s external shape is customized. To order the required shape, so please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S14634EJ1V0DS00 (1st edition)
Date Published February 2002 NS CP(K)
Printed in Japan
The mark
!
shows major revised points.
©
1999
µ
PD16781
5
1. BLOCK DIAGRAM
STHR
R,/L
CLK
1
to CLK
3
MODE
C
1
C
2
160-bit Shift Register
STHL
V
DD1
(3.3/5.0 V)
V
SS1
C
159
C
160
Level Shifter
V
DD2
(5.0 V)
V
SS2
C
1
C
2
C
3
CX
Sample And Hold
V
SS3
Input
TEST
S
1
S
2
S
479
S
480
2. SAMPLE-AND HOLD CIRCUIT AND OUTPUT CIRCUIT
SHPn
CX
S&H
1
SW
Video Line (C
n
)
C
H1
V
SS3
S
n
–
+
SW
SW
C
H1
V
SS3
S&H
2
–
+
SW
2
DataSheet S14634EJ1V0DS
µ
PD16781
3. PIN CONFIGURATION (
µ
PD16781N-xxx) (Copper Foil Surface, Face-up)
S
480
S
479
S
478
STHL
V
DD2
V
SS2
C
1
C
2
C
3
V
DD1
CLK
1
CLK
2
CLK
3
MODE
R,/L
CX
TEST
V
SS1
V
SS3
V
SS2
V
DD2
STHR
S
3
S
2
S
1
Copper foil
surface
Remark
This figure does not specify the TCP package.
DataSheet S14634EJ1V0DS
3
µ
PD16781
4. PIN FUNCTIONS
Pin Symbol
C
1
to C
3
S
1
to S
480
Pin Name
Video signal input
Video signal output
I/O
I
O
Description
These pins are input video signals R, G, and B.
These pins are output video signals, which have been sampled and hold.
The relationship between the video signal input (C
1
to C
3
) and video signal output is
shown below.
C
1
: S
3n−2
(n = 1, 2, ··········160)
C
2
: S
3n−1
C
3
: S
3n
STHR,
STHL
Cascade I/O
I/O
These pins are inputs/outputs for the start pulse for sample and hold timing.
High level of STHR/STHL is read at rising edge of CLK and start sampling video
signal. STHR serves as the input pin and STHL serves as output pin for the right
shift. For left shift, STHL serves as the input pins and STHR serves as the output
pin.
R,/L
Shift direction control
I
The shift direction control pin of shift register. The shift directions of the shift
registers are as follows.
R,/L = H (right shift): STHR input, S
1
→
S
480
, STHL output.
R,/L = L (left shift): STHL input, S
480
→
S
1
, STHR output.
CLK
1
to CLK
3
Shift clock input
I
The start pulse is read at rising edge of CLK. The sampling pulse SHPn is
generated at rising edge of CLK. For details, refer to
6. TIMING CHART.
The relationship between the clocks and the output pins is shown below.
(1) When MODE = L or open (sequential sampling)
CLK
1
R,/L = H: S
3n−2
R,/L = L: S
3n
CLK
2
: S
3n−1
CLK
3
R,/L = H: S
3n
R,/L = L: S
3n−2
(1) When MODE = H (simultaneous sampling)
CLK
1
: S
3n−2
, S
3n−1
, S
3n
(
n
= 1, 2,·····160)
CLK
2
: Connect V
DD1
or V
SS1
CLK
3
: Connect V
DD1
or V
SS1
MODE
Mode select signal input
I
This pin is used to select whether the three analog input signals, C
1
, C
2
, and C
3
are
sampled simultaneously or sequentially (This pin is pulled down in the IC).
MODE = H: Simultaneous sampling
MODE = L or open: Sequential sampling
CX
Hold capacitance control
input
I
Two Sample & hold circuits are switched.
CX = H S&H1: Sampling, S&H2: Output
CX = L S&H1: Output, S&H2: Sampling
TEST
V
DD1
V
DD2
V
SS1
V
SS2
V
SS3
Test
Logic power supply
Driver power supply
Logic ground
Driver ground
Sample & hold ground
I
−
−
−
−
−
Fix this pin to the L level.
3.0 to 5.5 V
5.0
±
0.5 V
Grounding
Grounding
It is ground of Sample & hold capacitance. Supply this terminal with the stable
GND.
4
DataSheet S14634EJ1V0DS
µ
PD16781
Cautions 1. To prevent latch-up-breakdown, the power should be turned on in order V
DD1
, Logic input V
DD2
,
video signal input. It should be turned off in the opposite order. This relationship should be
followed during transition periods as well.
2. The sampling of the video signal of this IC is only the simultaneous 3 output sampling of C
1
to C
3
.
Incidentally, it is designing abound of the input of the video signal in 10 MHz MAX.
If a video signal with a higher frequency is input, the data may not be correctly displayed.
3. Recommend a bypass capacitor of about 0.1
µ
F with good high-frequency characteristics between
5
V
DD1
and V
SS1
, and V
DD2
and V
SS2
in each driver IC. Unless the power supply is reinforced,
the supply voltage may fluctuate, making the sampling voltage abnormal.
4. If noise is superimposed on the start pulse pin, the data may not be displayed. For this reason,
be sure to input CX signal during the vertical blanking period.
5. If the start pulse width is extended by half the clock or longer, the sampling start timing SHP1 does
not change from normal timing; therefore, the sampling operation is performed normally.
5. FUNCTION DESCRIPTION
5.1 Switching of Sample & Hold Circuits
Two sample-and-hold circuits are switched.
CX
L
H
Output
Sample & Hold Circuit 1 (S&H
1
)
Sample & Hold Circuit 2 (S&H
2
)
Sample & hold operation
Sample & Hold Circuit 2 (S&H
2
)
Sample & Hold Circuit 1 (S&H
1
)
5.2 Sample & Hold and Output
Relation between video signals C
1
, C
2
and C
3
and output pins and two sample & hold circuits.
CX
L
Sampling
Output
H
Sampling
Output
S
1
(S
480
)
C
1-2
(C
3-2
)
C
1-1
(C
3-1
)
C
1-1
(C
3-1
)
C
1-2
(C
3-2
)
S
2
(S
479
)
C
2-2
(C
2-2
)
C
2-1
(C
2-1
)
C
2-1
(C
2-1
)
C
2-2
(C
2-2
)
S
3
(S
478
)
C
3-2
(C
1-2
)
C
3-1
(C
1-1
)
C
3-1
(C
1-1
)
C
3-2
(C
1-2
)
S
4
(S
477
)
C
1-2
(C
3-2
)
C
1-1
(C
3-1
)
C
1-1
(C
3-1
)
C
1-2
(C
3-2
)
···
···
···
···
···
S
479
(S
2
)
C
2-2
(C
2-2
)
C
2-1
(C
2-1
)
C
2-1
(C
2-1
)
C
2-2
(C
2-2
)
S
480
(S
1
)
C
3-2
(C
1-2
)
C
3-1
(C
1-1
)
C
3-1
(C
1-1
)
C
3-2
(C
1-2
)
Remark
C
m-n
= m: Video input, n: Sample & Hold
DataSheet S14634EJ1V0DS
5
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