White Electronic Designs
W3HG64M72EER-AD7
ADVANCED*
512MB – 64Mx72 DDR2 SDRAM REGISTERED, w/PLL,
VLP Mini-DIMM
FEATURES
244-pin, very low profile dual in-line memory
module (VLP Mini-DIMM)
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300*, and PC2-6400*
Supports ECC error detection and correction
V
CC
= V
CCQ
= 1.8V ±0.1V
V
CCSPD
= 1.7V to 3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL)
Posted CAS# additive latency (AL)
On-die termination (ODT)
Programmable burst lenghts: 4 or 8
Serial Presence Detect (SPD) with EEPROM
Auto and Self Refresh Capability (64ms: 8,192
cycle refresh)
Gold (Au) edge contacts
RoHS compliant
Single Rank
Package option
• 244 Pin Mini-DIMM
• PCB – 18.29mm (0.72")
DESCRIPTION
The W3HG64M72EER is a 64Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory
module consists of nine 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
244-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity option
OPERATING FREQUENCIES
PC2-3200
Clock Speed
CL-t
RCD
-t
RP
* Contact factory for availability
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
200MHz
3-3-3
December 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Symbol
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
RESET#
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
NC
V
CCQ
CKE0
V
CC
NC
NC/ERR_
OUT
V
CCQ
A11
A7
V
CC
A5
Pin No.
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
Symbol
A4
V
CCQ
A2
V
CC
V
SS
V
SS
NC/PAR_IN
V
CC
A10/AP
BA0
V
CC
WE#
V
CCQ
CAS#
V
CCQ
NC
NC
V
CCQ
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SA1
Pin No.
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
Symbol
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
NC
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
NC
V
SS
CB6
CB7
V
SS
NC
V
CCQ
NC
V
CC
NC
NC
V
CCQ
A12
A9
V
CC
A8
A6
Pin No.
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
Symbol
V
CCQ
A3
A1
V
CC
CK0
CK0#
V
CC
A0
BA1
V
CC
RAS#
V
CCQ
S0#
V
CCQ
ODT0
A13
V
CC
NC
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
NC
NC
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
SDA
SCL
V
CCSPD
W3HG64M72EER-AD7
ADVANCED
PIN NAMES
Pin Name
A0-A13
BA0,BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
DQS0#-DQS8#
ODT0
CK0,CK0#
CKE0
S0#
RAS#
CAS#
WE#
RESET#
DM (0-8)
V
CCSPD
V
CC
V
CCQ
A10/AP
V
SS
PAR_IN
ERR_OUT
SA0-SA2
SDA
SCL
NC
V
REF
Function
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
Data strobes
Data strobes complement
On-die termination control
Clock Inputs, positive line
Clock Enables
Chip Selects
Row Address Strobe
Column Address Strobe
Write Enable
Register Reset Input
Data Masks
SPD Power
Core Power
I/O Power
Address Input/Auto Precharge
Ground
Parity bit for the addess and control bus
Parity error found on the address and
control bus
SPD address
SPD Data Input/Output
Clock Input
No connect
Input/Output Reference
December 2005
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
RS0#
DQS0
DQS0#
DM0
DM/
RDQS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CS# DQS DQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
W3HG64M72EER-AD7
ADVANCED
DQS4
DQS4#
DM4
DM/
RDQS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS1#
DM1
DM/
RDQS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CS# DQS DQS#
DQS5
DQS5#
DM5
DM/
RDQS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CS# DQS DQS#
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS2
DQS2#
DM2
DM/
RDQS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CS# DQS DQS#
DQS6
DQS6#
DM6
DM/
RDQS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CS# DQS DQS#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS3
DQS3#
DM3
DM/
RDQS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CS# DQS DQS#
DQS7
DQS7#
DM7
DM/
RDQS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS8
DQS8#
DM8
DM/
RDQS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CS# DQS DQS#
V
CCSPD
V
CC
/V
CCQ
V
REF
V
SS
Serial PD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
Serial PD
SCL
WP A0
A1
A2
SDA
S0#
BA0 - BA1
A0 - A13
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
CK
CK#
R
E
G
I
S
T
E
R
RST#
RS0#
S0# DDR2 SDRAMs
BA0 - BA1 DDR2 SDRAMs
A0 - A13 DDR2 SDRAMs
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
Register
RBA0 - RBA1
RA0 - RA13
RRAS#
RCAS#
RWE#
RCKE0
RODT0
SA0 SA1 SA2
RAS# DDR2 SDRAMs
RCAS# DDR2 SDRAMs
WE# DDR2 SDRAMs
CKE0 DDR2 SDRAMs
ODT0 DDR2 SDRAMs
CK0#
RESET#
CK0
P
L
L
OE
NOTE: All resistor values are 22 ohms ±5% unless otherwise specified.
December 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
DC OPERATING CONDITIONS
All voltages referenced to V
SS
Parameter
Supply voltage
I/O Supply voltage
V
CCL
Supply voltage
I/O Reference voltage
I/O Termination voltage
Symbol
V
CC
V
CCQ
V
CCL
V
REF
V
TT
Min
1 .7
1 .7
1 .7
0.49 x V
CCQ
V
REF
-0.04
Typical
1 .8
1 .8
1 .8
0.50 x V
CCQ
V
REF
W3HG64M72EER-AD7
ADVANCED
Max
1 .9
1 .9
1 .9
0.51 x V
CCQ
V
REF
+ 0.04
Unit
V
V
V
V
V
Notes
1
4
4
2
3
Notes:
1. V
CC
and V
CCQ
must track each other. V
CCQ
must be less than or equal to V
CC
.
2. V
REF
is expected to equal V
CCQ
/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V
REF
may not excedd ±1 percent of the DC
value. Peak-to-peak AC noise on V
REF
may not exceed ±2 percent of V
REF
(DC). This measurement is to be taken at the nearest V
REF
bypass capacitor.
3. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
4. V
CCQ
tracks with V
CC
; V
CC
L track with V
CC
.
ABSOLUTE MAXIMUM DC RATINGS
Symbol
V
CC
V
CCQ
V
CCL
V
IN
, V
OUT
T
STG
T
CASE
T
OPR
Parameter
Voltage on V
CC
pin relative to V
SS
Voltage on V
CCQ
pin relative to V
SS
Voltage on V
CCL
pin relative to V
SS
Voltage on any pin relative to V
SS
Storage temperature
Device operating temperature
Operating temperature (ambient)
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
CK, CK#
DM
DQ, DQS, DQS#
MIN
-1.0
-0.5
-0.5
-0.5
-55
0
0
-5
-5
-5
-5
-18
MAX
2.3
2.3
2.3
2.3
100
85
55
5
5
5
5
18
U nit
V
V
V
V
°C
°C
°C
µA
µA
µA
µA
µA
I
L
Input leakage current; Any input 0V<V
IN
<V
CC
; V
REF
input
0V<V
IN
<0.95V; Other pins not under test = 0V
I
OZ
I
VREF
Output leakage current;
0V<V
OUT
<V
CCQ
; DQs and ODT are disable
V
REF
leakage current; V
REF
= Valid V
REF
level
INPUT/OUTPUT CAPACITANCE
TA=25 0 C, f=1 00MHz
Parameter
Input capacitance (A0 - A1 3, BA0 - BA1 ,RAS#,CAS#,WE#)
Input capacitance ( CKE0), (ODT0)
Input capacitance (CS0#)
Input capacitance (CK0, CK0#)
Input capacitance (DM0 - DM8), (DQS0 - DQS8)
Input capacitance (DQ0 - DQ63), (CB0 - CB7)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
OUT1
Min
Max
Unit
pF
pF
pF
pF
pF
pF
December 2005
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3HG64M72EER-AD7
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Operating temperature
Symbol
T
OPER
Rating
0°C to 85°C
Units
°C
Notes
V
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. Forthe measurement conditions, please refer to JEDEC JESD51 .2
2. At 0 - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Input High (Logic 1 ) Voltage
Input Low (Logic 0) Voltage
Symbol
V
IH
(DC)
V
IL
(DC)
Min
V
REF
+ 125
-300
Max
V
REF
+ 300
V
REF
- 125
Unit
mV
mV
INPUT AC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
AC Input High (Logic 1 ) Voltage (DDR2-400/533)
AC Input High (Logic 1) Voltage (DDR2-667)
AC Input Low (Logic 0) Voltage
Symbol
V
IH
(AC)
V
IH
(AC)
V
IL
(AC)
Min
V
REF
+ 250
V
REF
+ 200
—
V
REF
- 250
Max
—
Unit
mV
mV
mV
December 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com