áç
APRIL 2004
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 2.0.1
GENERAL DESCRIPTION
The XR16C864
1
(864) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 128 bytes of transmit and receive
FIFOs, transmit and receive FIFO counters and
trigger levels, automatic hardware and software flow
control, automatic RS-485 half-duplex direction
control and data rates of up to 2 Mbps. Each UART
has a set of registers that provide the user with
operating status and control, receiver error
indications, and modem serial interface controls.
System interrupts may be tailored to meet design
requirements. An internal loopback capability allows
onboard diagnostics. The 864 is available in the 100-
pin QFP package. The XR16C864 offers faster
channel status access by providing separate outputs
for TXRDY and RXRDY, offer separate Infrared TX
outputs and a separate clock input for channel C
(CHCCLK). The XR16C864 is compatible with the
industry standard ST16C554/554D, ST16C654/654D
and XR16C854/854D.
N
OTE
:
1 Covered by U.S. Patent #5,649,122 and #5,949,787.
FEATURES
Added feature in devices with top mark date code of
"F2 YYWW" and newer:
s
5 volt tolerant inputs
•
2.97 to 5.5 Volt Operation
•
Pin-to-pin compatible with the industry standard
ST16C554 and ST16C654 and TI’s TL16C554N
and TL16C754BFN
•
Intel or Motorola Data Bus Interface select
•
Four independent UART channels
s
s
s
s
s
s
s
s
s
Register Set Compatible to 16C550
Data rates of up to 2 Mbps
Transmit and Receive FIFOs of 128 bytes
Programmable TX and RX FIFO Trigger Levels
Transmit and Receive FIFO Level Counters
Automatic Hardware (RTS/CTS) Flow Control
Selectable Auto RTS Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Wireless Infrared (IrDA 1.0) Encoder/Decoder
•
Sleep Mode (200 uA typical)
•
Crystal oscillator or external clock input
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR16C864 B
LOCK
D
IAGRAM
A2:A0
D7:D0
IOR#
IOW #
CS# A-D
INT A-D
TXRDY# A-D
RXRDY# A-D
Reset
16/68#
INTSEL
CLKSEL
CHCCLK
TC
AEN
DACK A-D
TXDRQ # A-D
RXDRQ # A-D
XTAL1
XTAL2
BCLK A-D
Intel or
Motorola
Data Bus
Interface
5V tolerant inputs (except XTAL1)
2.97V to 5.5V VCC
UART Channel A
UART 128 Byte TX FIFO
Regs
BRG
IR
ENDEC
128 Byte RX FIFO
TX & RX
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#, OP2A#,
OP1A#/RS-485
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#, OP2B#,
OP1B#/RS-485
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#, OP2C#,
OP1C#/RS-485
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#, OP2D#,
OP1D#/RS-485
854 BLK
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
Direct
Memory
Access
UART Channel D
(same as Channel A)
Crystal Osc/Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
RXRDYD#/RXDRQD
RXRDYD#/RXDRQD
RXRDYA#/RXDRQA
RXA
TXRDYD#/TXDRQD
CDA#
TXRDYD#/TXDRQD
INTSEL
RID#
RID#
GND
GND
VCC
RXD
VCC
RXD
CDD#
RIA#
CDD#
D7
D6
D5
D4
D3
D2
D1
D0
87
86
85
84
83
82
81
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
RXRDYA#/RXDRQA
RXA
CDA#
GND
RIA#
D7
D6
D5
D4
D3
D2
D1
D0
99
98
97
96
95
94
93
92
91
90
89
88
100
BCLKA
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
BCLKC
OP2C#
OP1C#/RS-485
TC
AEN
OP1B#/RS-485
OP2B#
BCLKB
DACKC
DACKB
27
28
29
30
26
TXRDYC#/TXDRQC
TXRDYB#
25
IRTXC
IRTXB
24
DSRC#
DSRB#
23
CTSC#
CTSB#
22
DTRC#
DTRB#
21
VCC
GND
20
RTSC#
RTSB#
19
N.C.
INTB
18
A4
CSB#
17
TXC
TXB
16
N.C.
IOW#
15
TXD
TXA
14
N.C.
CSA#
13
N.C.
INTA
12
RTSD#
RTSA#
11
GND
VCC
10
DTRD#
DTRA#
9
CTSD#
CTSA#
8
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DSRD#
74
DSRA#
7
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
DSRC#
IRTXC
TXRDYC#/TXDRQC
DACKC
TC
OP1C#/RS-485
OP2C#
BCLKC
IRTXD
75
IRTXA
IRTXD
6
FSRS#
76
TXRDYA#/TXDRQA#
FSRS#
5
DACKD
77
DACKA
4
DACKD
OP1#/RS485
78
OP1A#/RS-485
OP1#/RS485
3
OP2D#
79
OP2A#
2
OP2D#
BCLKD
80
BCLKD
1
BCLKA
1
OP2A#
2
OP1A#/RS-485
3
DACKA
4
TXRDYA#/TXDRQA#
5
IRTXA
6
DSRA#
7
CTSA#
8
DTRA#
9
VCC
10
RTSA#
11
IRQ#
12
CS#
13
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
TXA
14
R/W#
15
F
IGURE
2. XR16C864 P
IN
O
UT
A
SSIGNMENT
I
N
16
AND
68 M
ODE
XR16C864
100-pin QFP
16 Mode
Connect 16/68# pin to VCC
XR16C864
100-pin QFP
68 Mode
Connect 16/68# pin to GND
2
45
46
47
48
49
50
31
32
33
34
35
36
37
38
39
40
41
A2
A1
A0
RXB
RXC
RIB#
CDC#
GND
RIC#
CDB#
XTAL1
XTAL2
16/68#
CLKSEL
TXRDY#
RXRDYB#/RXDRQB
RXRDYC#/RXDRQC
TXB
16
A3
17
N.C.
18
RTSB#
19
GND
20
DTRB#
21
CTSB#
22
DSRB#
23
IRTXB
24
TXRDYB#
25
DACKB
26
AEN
27
OP1B#/RS-485
28
OP2B#
29
BCLKB
30
áç
31
32
33
34
35
36
37
38
39
40
41
42
43
44
42
43
44
45
46
47
48
49
50
A2
A1
A0
RXB
RXC
CDC#
RIB#
GND
RIC#
XTAL1
XTAL2
16/68#
RESET
CLKSEL
RESET#
TXRDY#
RXRDY#
RXRDY#
CHCCLK
CHCCLK
CDB#
RXRDYB#/RXDRQB
RXRDYC#/RXDRQC
REV. 2.0.1
áç
REV. 2.0.1
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
ORDERING INFORMATION
P
ART
N
UMBER
XR16C864CQ
XR16C864IQ
P
ACKAGE
100-Lead QFP
100-Lead QFP
O
PERATING
T
EMPERATURE
R
ANGE
0°C to +70°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
PIN DESCRIPTIONS
Pin Description
N
AME
100-QFP
T
YPE
P
IN
#
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(N.C.)
37
38
39
95
94
93
92
91
90
89
88
66
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channels A-D during a data bus transaction.
I/O
Data bus lines [7:0] (bidirectional).
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes
read strobe (active low). The falling edge instigates an internal read cycle and retrieves
the data byte from an internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is not
used.
When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write
strobe (active low). The falling edge instigates the internal write cycle and the rising edge
transfers the data byte on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input
becomes read (logic 1) and write (logic 0) signal.
When 16/68# pin is at logic 1, this input is chip select A (active low) to enable channel A in
the device.
When 16/68# pin is at logic 0, this input becomes the chip select (active low) for the
Motorola bus interface.
When 16/68# pin is at logic 1, this input is chip select B (active low) to enable channel B in
the device.
When 16/68# pin is at logic 0, this input becomes address line A3 which is used for chan-
nel selection in the Motorola bus interface.
When 16/68# pin is at logic 1, this input is chip select C (active low) to enable channel C
in the device.
When 16/68# pin is at logic 0, this input becomes address line A4 which is used for chan-
nel selection in the Motorola bus interface.
IOW#
(R/W#)
15
I
CSA#
(CS#)
13
I
CSB#
(A3)
17
I
CSC#
(A4)
64
I
3
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
Pin Description
N
AME
CSD#
(N.C.)
INTA
(IRQ#)
100-QFP
T
YPE
P
IN
#
68
I
D
ESCRIPTION
áç
REV. 2.0.1
When 16/68# pin is at logic 1, this input is chip select D (active low) to enable channel D
in the device.
When 16/68# pin is at logic 0, this input is not used.
12
O When 16/68# pin is at logic 1 for Intel bus interface, this ouput becomes channel A inter-
(OD) rupt output. The output state is defined by the user and through the software setting of
MCR[3]. INTA is set to the active mode when MCR[3] is set to a logic 1. INTA is set to the
three state mode when MCR[3] is set to a logic 0 (default). See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes device inter-
rupt output (active low, open drain). An external pull-up resistor is required for proper
operation.
O
When 16/68# pin is at logic 1 for Intel bus interface, these ouputs become the interrupt
outputs for channels B, C, and D. The output state is defined by the user through the soft-
ware setting of MCR[3]. The interrupt outputs are set to the active mode when MCR[3] is
set to a logic 1 and are set to the three state mode when MCR[3] is set to a logic 0
(default). See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, these outputs are unused and
will stay at logic zero level. Leave these outputs unconnected.
Interrupt Select (active high, input with internal pull-down).
When 16/68# pin is at logic 1 for Intel bus interface, this pin can be used in conjunction
with MCR bit-3 to enable or disable the INT A-D pins or override MCR bit-3 and enable
the interrupt outputs. Interrupt outputs are enabled continuously by making this pin a
logic 1. Making this pin a logic 0 allows MCR bit-3 to enable and disable the interrupt out-
put pins. In this mode, MCR bit-3 is set to a logic 1 to enable the continuous output. See
MCR bit-3 description for full detail. This pin must be at logic 0 in the Motorola bus inter-
face mode.
UART channels A-D Transmitter Ready (active low). These outputs provide the TX FIFO/
THR status for transmit channels A-D. See
Table 5.
If Direct Memory Access is enabled,
these outputs become Transmit Direct Memory Access Request outputs. See TXDRQ pin
description for more details. If these outputs are unused, leave them unconnected.
UART channels A-D Receiver Ready (active low). These outputs provide the RX FIFO/
RHR status for receive channels A-D. See
Table 5.
If Direct Memory Access is enabled,
these outputs become Receive Direct Memory Access Request outputs. See RXDRQ pin
description for more details. If these outputs are unused, leave them unconnected.
Transmitter Ready (active low). This output is a logically wire-ORed status of TXRDY#
A-D. See
Table 5.
If this output is unused, leave it unconnected.
INTB
INTC
INTD
(N.C.)
18
63
69
INTSEL
87
I
TXRDYA#
TXRDYB#
TXRDYC#
TXRDYD#
RXRDYA#
RXRDYB#
RXRDYC#
RXRDYD#
TXRDY#
5
25
56
81
100
31
50
82
45
O
O
O
RXRDY#
44
O
Receiver Ready (active low). This output is a logically wire-ORed status of RXRDY# A-D.
See
Table 5.
If this output is unused, leave it unconnected.
FSRS#
76
I
FIFO Status Register Select (active low input with internal pull-up).
The content of the FSTAT register is placed on the data bus when this pin becomes
active. However it should be noted, D0-D3 contain the inverted logic states of TXRDY#
A-D pins, and D4-D7 the logic states (un-inverted) of RXRDY# A-D pins. Address line is
not required when reading this status register.
DIRECT MEMORY ACCESS INTERFACE
4
áç
REV. 2.0.1
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
Pin Description
N
AME
TC
AEN
100-QFP
T
YPE
P
IN
#
54
27
I
I
D
ESCRIPTION
Direct Memory Access Terminal Count. A high pulse terminates a Direct Memory Access
transaction. If Direct Memory Access is not used, this input should be connected to GND.
Address Enable for Direct Memory Access. A high at this input indicates a valid Direct
Memory Access cycle. See DACK pin descriptions below for Direct Memory Access cycle
description. If Direct Memory Access is not used, this input should be connected to GND.
Direct Memory Access Acknowledge. Direct Memory Access cycle will start processing
when CPU/Host sets this input low and AEN high. All writes will be to the TX FIFO and all
reads will be from the RX FIFO. A0-A2 and CS# A-D will be ignored. If Direct Memory
Access is not used, these inputs should be connected to VCC.
Transmit Direct Memory Access Request. A transmit empty request is indicated by a high
level on TXDRQ. The TXDRQ line is held high until either TC pulses or the TX FIFO is
filled above its trigger level. Transmit Direct Memory Access Request is enabled by set-
ting EMSR register bit-2 = 1. If Direct Memory Access is not used, leave these outputs
unconnected.
Receive Direct Memory Access Request. A Receive ready request is indicated by a high
level on RXDRQ. The RXDRQ line is held high until either TC pulses or the RX FIFO is
emptied. Receive Direct Memory Access Request is enabled by setting EMSR register
bit-3 = 1. If Direct Memory Access is not used, leave these outputs unconnected.
DACKA
DACKB
DACKC
DACKD
TXDRQA
TXDRQB
TXDRQC
TXDRQD
RXDRQA
RXDRQB
RXDRQC
RXDRQD
4
26
55
77
5
25
56
81
100
31
50
82
I
O
O
MODEM OR SERIAL I/O INTERFACE
TXA
TXB
TXC
TXD
IRTXA
IRTXB
IRTXC
IRTXD
RXA
RXB
RXC
RXD
RTSA#
RTSB#
RTSC#
RTSD#
CTSA#
CTSB#
CTSC#
CTSD#
14
16
65
67
6
24
57
75
97
34
47
85
11
19
62
70
8
22
59
73
O
UART channels A-D Transmit Data and infrared transmit data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic
1 during reset, or idle (no data). Infrared IrDA transmit and receive interface is enabled
when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0.
UART channels A-D Infrared Transmit Data. The inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. Regardless of the logic state of MCR bit-6, this pin
will be operating in the Infrared mode.
O
I
UART channels A-D Receive Data or infrared receive data. Normal receive data input
must idle at logic 1 condition. The infrared receiver pulses typically idles at logic 0 but can
be inverted by software control prior going in to the decoder, see FCTR[2].
O
UART channels A-D Request-to-Send (active low) or general purpose output. This output
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], FCTR[1:0],
EMSR[5:4] and IER[6]. Also see
Figure 10.
If these outputs are not used, leave them
unconnected.
UART channels A-D Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. Also see
Figure 10.
These inputs
should be connected to VCC when not used.
I
5
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