VBUS053AZ-HAF
www.vishay.com
Vishay Semiconductors
USB-OTG BUS-Port ESD Protection for V
BUS
= 12 V
FEATURES
• Ultra compact LLP75-7L package
6
5
4
• Low package height < 0.6 mm
• 3-line USB ESD protection with max. working
range = 5.5 V
7
• V
BUS
- protection with 12 V working range
21102
1
2
3
• Low leakage current
• Low load capacitance C
D
= 0.7 pF
20517
1
MARKING
(example only)
• ESD immunity to IEC 61000-4-2
± 15 kV contact discharge
± 15 kV air discharge
• Surge current acc. IEC 61000-4-5 I
PP
> 3 A
• e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
XX
YY
Dot = pin 1 marking
XX = date code
YY = type code (see table below)
21001
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
DESIGN SUPPORT TOOLS
click logo to get started
Models
Available
ORDERING INFORMATION
DEVICE NAME
VBUS053AZ-HAF
ORDERING CODE
VBUS053AZ-HAF-GS08
TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL)
15 000
MINIMUM ORDER QUANTITY
15 000
PACKAGE DATA
DEVICE NAME
VBUS053AZ-HAF
PACKAGE
NAME
LLP75-7L
TYPE
CODE
U9
WEIGHT
4.2 mg
MOLDING COMPOUND
FLAMMABILITY RATING
UL 94 V-0
MOISTURE
SENSITIVITY LEVEL
MSL level 1
(according J-STD-020)
SOLDERING
CONDITIONS
260 °C/10 s at terminals
ABSOLUTE MAXIMUM RATINGS VBUS053AZ-HAF
PARAMETER
Peak pulse current
Peak pulse power
ESD immunity
V
BUS
: Pin 6 to ground (pin 7)
Peak pulse current
Peak pulse power
ESD immunity
Operating temperature
Storage temperature
Rev. 1.6, 03-May-17
acc. IEC 61000-4-5; tp = 8/20 μs/single shot
acc. IEC 61000-4-5; tp = 8/20 μs/single shot
Contact discharge acc. IEC 61000-4-2; 10 pulses
Air discharge acc. IEC 61000-4-2; 10 pulses
Junction temperature
I
PPM
P
PP
V
ESD
T
J
T
STG
8
240
± 30
± 30
-40 to +125
-55 to +150
A
W
kV
°C
°C
TEST CONDITIONS
acc. IEC 61000-4-5; t
p
= 8/20 μs; single shot
acc. IEC 61000-4-5; t
p
= 8/20 μs; single shot
Contact discharge acc. IEC 61000-4-2; 10 pulses
Air discharge acc. IEC 61000-4-2; 10 pulses
SYMBOL
I
PPM
P
PP
V
ESD
VALUE
3
36
± 15
± 15
UNIT
A
W
kV
Data line D+, D-, ID: Pin 1, 2 and 3 to ground (pin 7)
Document Number: 81845
1
For technical questions, contact:
ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VBUS053AZ-HAF
www.vishay.com
Vishay Semiconductors
TEST CONDITIONS/REMARKS
SYMBOL
N
channel
V
RWM
I
R
I
R
V
F
V
BR
V
C
V
C
V
F
C
D
dC
D
C
DD
MIN.
-
-
-
-
0.7
6.5
-
-
-
-
-
-
TYP.
-
-
-
-
-
-
10
15
3.4
0.7
-
0.35
MAX.
3
5.5
0.085
1
1.2
10
12
18
4.1
1
0.1
0.5
UNIT
lines
V
μA
μA
V
V
V
V
V
pF
pF
pF
ELECTRICAL CHARACTERISTICS VBUS053AZ-HAF
All inputs (pin 1, 2, and 3) to ground (pin 7)
PARAMETER
Protection paths
Reverse stand-off voltage
Reverse current
Forward voltage
Reverse breakdown voltage
Reverse clamping voltage
Forward clamping voltage
Line capacitance
Line symmetry
Line to line capacitance
Number of lines which can be protected
at I
R
= 0.1 μA
at V
R
= V
RWM
= 3.3 V; T = 65 °C
at V
R
= V
RWM
= 5.5 V
at I
F
= 15 mA
at I
R
= 1 mA
at I
PP
= 1 A; acc. IEC 61000-4-5; T = 25 °C
at I
PP
= 3 A; acc. IEC 61000-4-5; T = 25 °C
at I
F
= 3 A; acc. IEC 61000-4-5
Test pin at V
R
= 0 V;
any other I/O pin at V
R
= 3.3 V, f = 1 MHz
Difference of the line capacitance
Among pins 1, 2 and 3
at V
R
= 0 V; f = 1 MHz
Note
• T
amb
= - 40 °C to 85 °C, unless otherwise specified
ELECTRICAL CHARACTERISTICS
V
BUS
(pin 6) to ground (pin 7)
PARAMETER
Protection paths
Reverse working voltage
Reverse current
Forward voltage
Reverse breakdown voltage
Reverse clamping voltage
Forward clamping voltage
Line capacitance
TEST CONDITIONS/REMARKS
Number of line which can be protected
at I
R
= 100 nA
at V
R
= V
RWM
= 12 V
at I
F
= 10 mA
at I
R
= 1 mA
at I
PP
= 1 A; acc. IEC 61000-4-5; T = 25 °C
at I
PP
= 8 A; acc. IEC 61000-4-5; T = 25 °C
at I
F
= 8 A; acc. IEC 61000-4-5
at V
R
= 0 V, f = 1 MHz
SYMBOL
N
channel
V
RWM
I
R
V
F
V
BR
V
C
V
C
V
F
C
D
MIN.
-
12
-
0.6
15
-
-
-
-
TYP.
-
-
-
0.75
-
17.5
25
-
70
MAX.
1
-
100
0.9
18
20
30
2.2
85
UNIT
line
V
nA
V
V
V
V
V
pF
Note
• T
amb
= -40 °C to +85 °C, unless otherwise specified
Rev. 1.6, 03-May-17
Document Number: 81845
2
For technical questions, contact:
ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VBUS053AZ-HAF
www.vishay.com
APPLICATION NOTE
The VBUS053AZ-HAF is intended as an ESD protection and transient voltage suppressor for one USB-OTG port.
The LLP75-7L package contains two separate dies which are mounted on a common ground plane (pin 7). The high-speed data
lines D-, D+ and ID, are connected to any of the pins no. 1 to 3. As long as the signal voltage on the data lines is between the
ground- and the 5 V working range, the low capacitance PN-diodes offer a very high isolation to ground and to the other data
lines. But as soon as any transient signal like an ESD signal, exceeds this working range of 5 V in either the positive or negative
direction, one of the PN-diodes gets into the forward mode and clamps the transient either to ground or to the avalanche break
through level. An extra avalanche diode (separate die) clamps the supply line voltage (V
BUS
at pin 6) above the 12 V working
range to ground (pin 7).
Due to the “two die construction” the V
BUS
line has a very high isolation to the data lines. In case of a destructive transient signal,
i.e. coming from a charger, the data lines will not be influenced.
V
BUS
6
(pinning top view)
5
4
nc. nc.
6
7
GND
7
3
ID
1
2
3
5
4
Vishay Semiconductors
1
D-
2
D+
21103
Remark:
The input pins no. 1, 2 and 3 are symmetrical. Each of the data signals D-, D+ and ID can be connected to pin 1, 2 or 3
TYPICAL CHARACTERISTICS
(T
amb
= 25 °C, unless otherwise specified)
120 %
Rise time = 0.7 ns to 1 ns
100 %
80 %
60 %
53 %
80
f = 1 MHz
70
60
Pin 6 to pin 7
Discharge Current I
ESD
C
D
(pF)
50
40
30
20
10
40 %
27 %
20 %
0%
-10 0 10 20 30 40 50 60 70 80 90 100
0
21468
0
5
10
15
20557
Time (ns)
V
R
(V)
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330
/150
pF)
Fig. 3 - Typical Capacitance C
D
vs. Reverse Voltage V
R
0.8
100 %
80 %
60 %
8 µs to 100 %
f = 1 MHz, one I/O pin at 3.3 V
0.7
0.6
C
D
(pF)
0.5
0.4
0.3
Pin 1, 2 or 3 to pin 7
0.2
I
PPM
20 µs to 50 %
40 %
20 %
0.1
0%
0
20548
0
10
20
30
40
21469
0
0.5
1
1.5
2
2.5
3
3.5
Time (µs)
V
R
(V)
Fig. 2 - 8/20 μs Peak Pulse Current Wave Formacc. IEC 61000-4-5
Rev. 1.6, 03-May-17
Fig. 4 - Typical Capacitance C
D
vs. Reverse Voltage V
R
Document Number: 81845
3
For technical questions, contact:
ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VBUS053AZ-HAF
www.vishay.com
Vishay Semiconductors
30
Measured acc. IEC 61000-4-5
(8/20 µs - wave form)
100
10
Pin 6 to pin 7
25
P in 6 to p in 7
20
I
F
(mA)
V
C
(V)
1
Pin 1, 2 or 3 to pin 7
0.1
15
10
V
C
0.01
5
P in 7 to p in 6
0
0.6
0.7
0.8
0.9
1
1.1
21473
0.001
0.5
21470
0
1
2
3
4
5
6
7
8
9 10 11
V
F
(V)
I
PP
(A)
Fig. 5 - Typical Forward Current I
F
vs. Forward Voltage V
F
Fig. 8 - Typical Peak Clamping Voltage V
C
vs.
Peak Pulse Current I
PP
20
18
16
14
Pin 6 to pin 7
V
R
(V)
12
10
8
6
4
2
0
0.01
0.1
1
10
100
1000 10 000
Pin 1, 2 or 3 to pin 7
21471
I
R
(µA)
Fig. 6 - Typical Reverse Voltage V
R
vs. Reverse Current I
R
18
Measured acc. IEC 61000-4-5 (8/20 µs - wave form)
16
14
12
P in 1 , 2 o r 3 to p in 7
V
C
(V)
10
8
6
4
2
0
0
1
2
3
4
P in 7 to p in 1 , 2 o r 3
V
F
21472
I
PP
(A)
Fig. 7 - Typical Peak Clamping Voltage V
C
vs.
Peak Pulse Current I
PP
Rev. 1.6, 03-May-17
Document Number: 81845
4
For technical questions, contact:
ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VBUS053AZ-HAF
www.vishay.com
PACKAGE DIMENSIONS
in millimeters (inches):
LLP75-7L
0.3 (0.012)
1.05 (0.041)
0.95 (0.037)
Vishay Semiconductors
Heat sink
0.2 (0.008)
0.3 (0.012)
0.2 (0.008)
0.3 (0.012)
0.55 (0.022)
0.45 (0.018)
1 (0.039)
0.5 (0.020)
0.6 (0.024)
0.25 (0.010)
0.15 (0.006)
0.6 (0.024)
1.65 (0.065)
Pin 1 marking
1.55 (0.061)
1.65 (0.065)
Foot print recommendation:
0.5 (0.020)
0.3 (0.012)
0.15 (0.006)
0.5 (0.020)
0.3 (0.012)
0.15 (0.006)
0.25 (0.010)
1 (0.039)
0.5 (0.020)
1 (0.039)
1.55 (0.061)
0.54 (0.021)
0.05 (0.002)
0 (0.000)
0.2 (0.008)
Solder resist mask
Document no.:S8-V-3906.02-014 (4)
Created - Date: 04. April 2006
20500
Solder pad
0.5 (0.020)
Rev. 1.6, 03-May-17
Document Number: 81845
5
For technical questions, contact:
ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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