DATASHEET
ISL29501
Time of Flight (ToF) Signal Processing IC
the
ISL29501
is a Time of Flight (ToF) based signal processing
integrated circuit. The sensor enables low cost, low power, and
long range optical distance sensing when combined with an
external emitter and detector.
The ISL29501 has a built-in current DAC circuit that drives an
external LED or laser. The modulated light from the emitter is
reflected off the target and is received by the photodiode. The
photodiode then converts the returned signal into current,
which is used by the ISL29501 for signal processing.
An on-chip Digital Signal Processor (DSP) calculates the time
of flight, which is proportional to the target distance. The
ISL29501 is equipped with an I
2
C interface for configuration
and control.
Use of an external photodiode and emitter allows the user to
optimize the system design for performance, power
consumption, and distance measurement range that suit their
industrial design.
The ISL29501 is wavelength agnostic and permits the use of
other optical wavelengths if better suited for applications.
FN8681
Rev.5.00
May 5, 2017
Features
• Enables proximity detection and distance measurement
• Modulation frequency of 4.5MHz
• Emitter DAC with programmable current up to 255mA
• Operates in Continuous and Single Shot mode
• On-chip active ambient light rejection
• Auto gain control mechanism
• Interrupt controller
• Supply voltage range of 2.7V to 3.3V
• I
2
C interface supporting 1.8V and 3.3V bus
• Low profile 24 Ld 4x5 QFN package
Applications
• Mobile consumer applications
• Industrial proximity sensing
• Power management
• Home automation
Related Literature
• For a full list of related documents, visit our website
-
ISL29501
product page
2.7V TO 3.3V
2.7V TO 3.3V
C
1
R
4
R
1
R
2
R
3
R
5
A1
A2
SCL
SDA
HOST
MCU
IRQ
SS
CEn
VOUT
AVDD
C
4
AVCC
AVSS
RSET
R
4
C
3
PDp
PD
PDn
EVSS
DVCC
DVSS
EVCC
EIR
IR
LED
C
2
2.7V TO 3.3V
FIGURE 1. APPLICATION DIAGRAM
FN8681 Rev.5.00
May 5, 2017
Page 1 of 22
ISL29501
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I
2
C Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Principles of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (CEn) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Sample Start (SS) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interrupt (IRQ) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Sampling Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Single Shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Continuous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Emitter Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
EIR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Main DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Threshold DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connecting the Photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Selecting the Photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Emitter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ambient Light Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sampling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Light ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
12
12
12
Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I
2
C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Identification (Address) . . . . . . . . . . . . . . . . . . . . . . . . . .
A2 and A1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protocol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
13
14
14
Standard Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Crosstalk Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Distance Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Optical System Design Considerations. . . . . . . . . . . . . . . . 15
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PCB Design Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 20
The QFN Package Requires Additional PCB Layout Rules for
the Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
General Power PAD Design Considerations . . . . . . . . . . . . 20
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FN8681 Rev.5.00
May 5, 2017
Page 2 of 22
ISL29501
Block Diagram
AVCC
RSET
DVDD
PDp
-
Av
BPF
+
A TO D
CONVERTER
SCL
SDA
I C
2
PDn
IRQ
SS
EIR
EMITTER
DRIVER
EVSS
OSCILLATOR
DIGITAL
CALIBRATION
AND
PROCESSING
EVCC
AVSS
DVSS
FIGURE 2. BLOCK DIAGRAM
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ISL29501IRZ-T7
ISL29501IRZ-T7A
ISL29501-ST-EV1Z
ISL29501-CS-EVKIT1Z
NOTES:
1. Refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see device information page for
ISL29501.
For more information on MSL, see techbrief
TB477.
PART
MARKING
29501 IRZ
29501 IRZ
V
DD
RANGE
(V)
2.7V to 3.3V
2.7V to 3.3V
TEMP RANGE
(°C)
-40 to +85
-40 to +85
TAPE AND REEL
(UNITS)
1k
250
PACKAGE
(RoHS COMPLIANT)
24 Ld QFN
24 Ld QFN
PKG.
DWG. #
L24.4x5F
L24.4x5F
Sand Tiger Evaluation Board
Cat Shark Evaluation Board
FN8681 Rev.5.00
May 5, 2017
Page 3 of 22
ISL29501
Pin Configuration
ISL29501
(24 LD QFN)
TOP VIEW
24 RSET
23 AVSS
20 AVSS
19 AVDD
18 VOUT
17 AVCC
EPAD
16 AVSS
15 DVSS
14 DVCC
13 AVSS
EVSS 10
EVCC 12
IRQ 8
EIR 11
SS 9
22 PDn
21 PDp
AVSS 1
AVSS 2
CEn 3
A2 4
SDA 5
SCL 6
A1 7
Pin Descriptions
PIN #
1, 2, 13
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20, 23
21
22
24
PIN NAME
AVSS
CEn
A2
SDA
SCL
A1
IRQ
SS
EVSS
EIR
EVCC
DVCC
DVSS
AVSS
AVCC
VOUT
AVDD
AVSS
PDp
PDn
RSET
EPAD
Tie to AVSS
Chip enable, active low
I
2
C address bit, pull to DVCC or DVSS.
I
2
C data bus
I
2
C clock bus
I
2
C ID address bit, pull to DVCC or DVSS.
Interrupt, active low, open-drain output signal to host. A 2.7kΩ pull-up to supply is required.
Sample start: input signal with HIGH to LOW edge active.
Emitter driver ground. Connects to cathode of emitter.
Emitter driver output. Connects to anode of emitter.
Emitter driver supply. Decouple with 2.2µF or larger capacitor along with a 0.1µF for high frequency.
Digital power 2.7V to 3.3V supply
Digital power ground
Analog power ground
Analog power 2.7 to 3.3V supply
AFE LDO output, tied to AVDD, decouple with 1µF and 0.01µF capacitor pair.
AFE analog supply
Analog ground shield
Photodiode cathode input
Photodiode anode input
Sets chip bias current. Tie to 10kΩ resistor 1% to AVSS ground.
Center EPAD: Tied to AVSS
DESCRIPTION
FN8681 Rev.5.00
May 5, 2017
Page 4 of 22
ISL29501
Absolute Maximum Ratings
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 4V
Voltage on All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . (-0.3V to V
CC
) + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114E) (Note
6)
. . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Latch-Up (Tested per JESD-78C; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
QFN Package (Notes
4, 5)
. . . . . . . . . . . . .
35
1.2
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
6. ESD HBM passed 2kV with exception to pins IRQ and SDA, which passed 1kV.
Electrical Specifications
PARAMETER
SENSOR PARAMETERS
Modulation Frequency
Chip Power Supply
Delay from Chip Enable to First Sample
Unless otherwise indicated, all the following tables are at DVCC, AVCC, and EVCC at 3V, T
A
= +25°C. Boldface
limits apply across the operating temperature range, -40°C to +85°C.
SYMBOL
TEST CONDITIONS
MIN
(Note
8)
TYP
MAX
(Note
8)
UNIT
f
mod
DVCC, AVCC,
EVCC
tcen_fs
tsleep_fs
I
S-HS
I
S-SD
IDDact
Modulation frequency of emitter
4.45
2.7
4.5
3.0
500
4.65
3.3
MHz
V
µs
Note 7
Note 7
CEn = 1; I
2
C disable; register values are
retained; SS = SDA = SCL = V
CC
CEn = 0; I
2
C enable; register values are
retained; all other functions are disabled
Emitter duty cycle = 50%, 0x90 = 06h,
0x91 = 00h
Delay between Sleep Mode to Start of First Sample
Quiescent Current - Sleep Mode,
DVCC+AVCC+EVCC
Quiescent Current - Shutdown, DVCC+AVCC+EVCC
Chip Current While Measuring, DVCC+AVCC+EVCC
AFE SPECIFICATIONS
Maximum AFE Input Current PDp/PDn
Voltage at PDp
Voltage at PDn
Low Noise Amplifier
Differential I to V Conversion Range
Maximum Photodiode Capacitance
Recommended
3
2.5
1
55
µs
µA
µA
mA
Imax_PD
VPDp
VPDn
LNA
TIA Gain
Cmax
Design recommendation
12.8
1.7
0.75
µA
V
V
N/A
kΩ
15
pF
Provides unity gain
0x97[0:1], b0 = 0 and b1 = 0 default
Design recommendation
1x
8k
FN8681 Rev.5.00
May 5, 2017
Page 5 of 22
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