ADSP-21160NCB-100 datasheet, PDF

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ADSP-21160NCB-100: DescriptionDigital Signal Processors & Controllers - DSP, DSC High Perf 32B 100MHz; Categorysemiconductor The embedded processor and controller; File Size1MB，58 Pages; ManufacturerADI; Websitehttps://www.analog.com

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ADSP-21160NCB-100 Overview

Digital Signal Processors & Controllers - DSP, DSC High Perf 32B 100MHz

ADSP-21160NCB-100 Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	ADI
Product Category	Digital Signal Processors & Controllers - DSP, DSC
RoHS	N
Mounting Style	SMD/SMT
Package / Case	BGA-400
Product	DSPs
Core	SHARC
Maximum Clock Frequency	100 MHz
Program Memory Size	4 MB
Data RAM Size	512 kB
Operating Supply Voltage	2.37 V to 2.63 V
Maximum Operating Temperature	+ 100 C
Packaging	Tray
Height	1.72 mm
Length	27 mm
Width	27 mm
Data Bus Width	32 bit
Minimum Operating Temperature	- 40 C
Moisture Sensitive	Yes
Factory Pack Quantity	40

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SHARC

Digital Signal Processor

ADSP-21160M/ADSP-21160N

SUMMARY

High performance 32-bit DSP—applications in audio, medi-

cal, military, graphics, imaging, and communication

Super Harvard architecture—4 independent buses for dual

data fetch, instruction fetch, and nonintrusive, zero-over-

head I/O

Backward compatible—assembly source level compatible

with code for ADSP-2106x DSPs

Single-instruction, multiple-data (SIMD) computational

architecture—two 32-bit IEEE floating-point computation

units, each with a multiplier, ALU, shifter, and register file

Integrated peripherals—integrated I/O processor, 4M bits

on-chip dual-ported SRAM, glueless multiprocessing fea-

tures, and ports (serial, link, external bus, and JTAG)

FEATURES

100 MHz (10 ns) core instruction rate (ADSP-21160N)

Single-cycle instruction execution, including SIMD opera-

tions in both computational units

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping and single-cycle loop setup, provid-

ing efficient program sequencing

IEEE 1149.1 JTAG standard Test Access Port and on-chip

emulation

400-ball 27 mm

27 mm PBGA package

Available in lead-free (RoHS compliant) package

200 million fixed-point MACs sustained performance

(ADSP-21160N)

CORE PROCESSOR

TIMER

INSTRUCTION

CACHE

32 x 48-BIT

DUAL-PORTED SRAM

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT

ADDR

DATA

ADDR

DATA

BLOCK 0

JTAG

BLOCK 1

TEST AND

EMULATION

I/O PORT

DATA

ADDR

DATA

ADDR

DAG1

8 x 4 x 32

DAG2

8 x 4 x 32

PROGRAM

SEQUENCER

IOD

IOA

EXTERNAL

PORT

ADDR BUS

MUX

MULTIPROCESSOR

INTERFACE

DATA BUS

MUX

HOST PORT

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

BUS

CONNECT

(PX)

DM DATA BUS

16/32/40/48/64

32/40/64

MULT

DATA

FILE

(PEX)

16 x 40-BIT

BARREL

SHIFTER

BARREL

SHIFTER

DATA

FILE

(PEY)

16 x 40-BIT

MULT

IOP

REGISTERS

(MEMORY

MAPPED)

CONTROL,

STATUS AND

DATA BUFFERS

DMA

CONTROLLER

SERIAL PORTS

(2)

LINK PORTS

(6)

ALU

I/O PROCESSOR

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. D

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADSP-21160NCB-100 Related Products

	ADSP-21160NCB-100	PFC-UD1206-03-3522-3522-D-B-1	ADSP-21160NCBZ-100	ADSP-21160MKBZ-80	ADSP-21160NKBZ-100
Description	Digital Signal Processors & Controllers - DSP, DSC High Perf 32B 100MHz	Array/Network Resistor, Divider, 0.5% +/-Tol, 25ppm/Cel, Surface Mount, 0612, CHIP	Digital Signal Processors & Controllers - DSP, DSC High Perf 32B 100MHz	Digital Signal Processors & Controllers - DSP, DSC 80MHz 600 MFLOPS 3.3V I/O Floating Pt	Digital Signal Processors & Controllers - DSP, DSC High Perf 32B 100MHz
Is it lead-free?	-	Contains lead	Contains lead	Contains lead	Lead free
Is it Rohs certified?	-	incompatible	conform to	conform to	conform to
package instruction	-	, 0612	BGA, BGA400,20X20,50	BGA, BGA400,20X20,50	BGA, BGA400,20X20,50
Reach Compliance Code	-	compliant	compliant	compliant	compliant
ECCN code	-	EAR99	3A991.A.2	3A991.A.2	3A991.A.2
Other features	-	ULTRA PRECISION	ALSO REQUIRES 3.3V SUPPLY	-	ALSO REQUIRES 3.3V SUPPLY
JESD-609 code	-	e0	e1	e1	-
Number of terminals	-	3	400	400	400
Maximum operating temperature	-	125 °C	-	85 °C	85 °C
Package shape	-	RECTANGULAR PACKAGE	SQUARE	SQUARE	SQUARE
Package form	-	SMT	GRID ARRAY	GRID ARRAY	GRID ARRAY
surface mount	-	YES	YES	YES	YES
technology	-	THIN FILM	CMOS	CMOS	CMOS
Terminal surface	-	Tin/Lead (Sn/Pb) - with Nickel (Ni) barrier	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	-
Parts packaging code	-	-	BGA	BGA	BGA
Contacts	-	-	400	400	400
Address bus width	-	-	32	32	32
barrel shifter	-	-	YES	YES	YES
bit size	-	-	32	32	32
boundary scan	-	-	YES	YES	YES
maximum clock frequency	-	-	50 MHz	80 MHz	50 MHz
External data bus width	-	-	64	64	64
Format	-	-	FLOATING POINT	FLOATING POINT	FLOATING POINT
Internal bus architecture	-	-	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	-	-	S-PBGA-B400	S-PBGA-B400	S-PBGA-B400
length	-	-	27 mm	27 mm	27 mm
low power mode	-	-	NO	YES	NO
Package body material	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	-	BGA	BGA	BGA
Encapsulate equivalent code	-	-	BGA400,20X20,50	BGA400,20X20,50	BGA400,20X20,50
Peak Reflow Temperature (Celsius)	-	-	260	260	NOT SPECIFIED
power supply	-	-	1.9,3.3 V	2.5,3.3 V	1.9,3.3 V
Certification status	-	-	Not Qualified	Not Qualified	Not Qualified
RAM (number of words)	-	-	131072	131072	131072
Maximum seat height	-	-	2.49 mm	2.49 mm	2.49 mm
Maximum supply voltage	-	-	2 V	2.63 V	2 V
Minimum supply voltage	-	-	1.8 V	2.37 V	1.8 V
Nominal supply voltage	-	-	1.9 V	2.5 V	1.9 V
Terminal form	-	-	BALL	BALL	BALL
Terminal pitch	-	-	1.27 mm	1.27 mm	1.27 mm
Terminal location	-	-	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	-	-	30	30	NOT SPECIFIED
width	-	-	27 mm	27 mm	27 mm
uPs/uCs/peripheral integrated circuit type	-	-	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER

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