74LVC1G07GV datasheet, PDF - EEWORLD Datasheet

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74LVC1G07GV: DescriptionLVC/LCX/Z SERIES, 1-INPUT NON-INVERT GATE, PDSO5; Categorylogic logic; File Size76KB，15 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/; Environmental Compliance

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74LVC1G07GV Overview

LVC/LCX/Z SERIES, 1-INPUT NON-INVERT GATE, PDSO5

74LVC1G07GV Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Philips Semiconductors (NXP Semiconductors N.V.)
package instruction	TSOP, TSOP5/6,.11,37
Reach Compliance Code	unknow
JESD-30 code	R-PDSO-G5
JESD-609 code	e3
Logic integrated circuit type	BUFFER
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of terminals	5
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-DRAIN
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP
Encapsulate equivalent code	TSOP5/6,.11,37
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
method of packing	TAPE AND REEL
power supply	3.3 V
Certification status	Not Qualified
Schmitt trigger	NO
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.95 mm
Terminal location	DUAL

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INTEGRATED CIRCUITS

DATA SHEET

74LVC1G07

Buffer with open-drain output

Product speciﬁcation

Supersedes data of 2003 Mar 07

2004 Sep 07

74LVC1G07GV Related Products

	74LVC1G07GV	74LVC1G07GM	74LVC1G07	74LVC1G07GW
Description	LVC/LCX/Z SERIES, 1-INPUT NON-INVERT GATE, PDSO5	LVC/LCX/Z SERIES, 1-INPUT NON-INVERT GATE, PDSO5	8-Bit Addressable Latches 16-SOIC -40 to 85	LVC/LCX/Z SERIES, 1-INPUT NON-INVERT GATE, PDSO5
Is it Rohs certified?	conform to	incompatible	-	conform to
Maker	Philips Semiconductors (NXP Semiconductors N.V.)	Philips Semiconductors (NXP Semiconductors N.V.)	-	Philips Semiconductors (NXP Semiconductors N.V.)
package instruction	TSOP, TSOP5/6,.11,37	SON, SOLCC6,.04,20	-	TSSOP, TSSOP5/6,.08
Reach Compliance Code	unknow	unknow	-	unknow
JESD-30 code	R-PDSO-G5	R-PDSO-N6	-	R-PDSO-G5
JESD-609 code	e3	e0	-	e3
Logic integrated circuit type	BUFFER	BUFFER	-	BUFFER
MaximumI(ol)	0.024 A	0.024 A	-	0.024 A
Number of terminals	5	6	-	5
Maximum operating temperature	125 °C	125 °C	-	125 °C
Minimum operating temperature	-40 °C	-40 °C	-	-40 °C
Output characteristics	OPEN-DRAIN	OPEN-DRAIN	-	OPEN-DRAIN
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	TSOP	SON	-	TSSOP
Encapsulate equivalent code	TSOP5/6,.11,37	SOLCC6,.04,20	-	TSSOP5/6,.08
Package shape	RECTANGULAR	RECTANGULAR	-	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL	TAPE AND REEL	-	TR
power supply	3.3 V	3.3 V	-	3.3 V
Certification status	Not Qualified	Not Qualified	-	Not Qualified
Schmitt trigger	NO	NO	-	NO
Nominal supply voltage (Vsup)	3.3 V	3.3 V	-	3.3 V
surface mount	YES	YES	-	YES
technology	CMOS	CMOS	-	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	-	AUTOMOTIVE
Terminal surface	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	-	Matte Tin (Sn)
Terminal form	GULL WING	NO LEAD	-	GULL WING
Terminal pitch	0.95 mm	0.5 mm	-	0.635 mm
Terminal location	DUAL	DUAL	-	DUAL

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