74AUP1G97
Rev. 10 — 28 March 2017
Low-power configurable multiple function gate
Product data sheet
1
General description
The 74AUP1G97 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR,
NAND, NOR, inverter and buffer. All inputs can be connected to V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
The 74AUP1G97 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The
difference between the positive voltage V
T+
and the negative voltage V
T-
is defined as the
input hysteresis voltage V
H
.
2
Features and benefits
•
Wide supply voltage range from 0.8 V to 3.6 V
•
High noise immunity
•
ESD protection:
–
HBM JESD22-A114F exceeds 5000 V
–
MM JESD22-A115-A exceeds 200 V
–
CDM JESD22-C101E exceeds 1000 V
•
Low static power consumption; I
CC
= 0.9 μA (maximum)
•
Latch-up performance exceeds 100 mA per JESD 78 Class II
•
Inputs accept voltages up to 3.6 V
•
Low noise overshoot and undershoot < 10 % of V
CC
•
I
OFF
circuitry provides partial power-down mode operation
•
Multiple package options
•
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
Low-power configurable multiple function gate
74AUP1G97
3
Ordering information
Package
Temperature
range
Name
SC-88
XSON6
XSON6
XSON6
XSON6
X2SON6
WLCSP6
Table 1. Ordering information
Type number
Description
plastic surface-mounted package; 6 leads
plastic extremely thin small outline package; no leads;
6 terminals; body 1 x 1.45 x 0.5 mm
plastic extremely thin small outline package; no leads;
6 terminals; body 1 x 1 x 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
plastic thermal extremely thin small outline package;
no leads; 6 terminals; body 1 x 0.8 x 0.35 mm
wafer level chip-scale package; 6 bumps;
0.65 x 0.44 x 0.27 mm
Version
SOT363
SOT886
SOT891
SOT1115
SOT1202
SOT1255
SOT1454-1
74AUP1G97GW
74AUP1G97GM
74AUP1G97GF
74AUP1G97GN
74AUP1G97GS
74AUP1G97GX
74AUP1G97UK
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
4
Marking
Marking code
aV
aV
aV
aV
aV
aV
7
[1]
Table 2. Marking
Type number
74AUP1G97GW
74AUP1G97GM
74AUP1G97GF
74AUP1G97GN
74AUP1G97GS
74AUP1G97GX
74AUP1G97UK
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 10 — 28 March 2017
2 / 25
Nexperia
Low-power configurable multiple function gate
74AUP1G97
5
Functional diagram
A
3
4
B
1
Y
C
6
001aad998
Figure 1. Logic symbol
6
Pinning information
6.1 Pinning
74AUP1G97
74AUP1G97
B
GND
A
1
2
3
001aad999
B
1
6
C
6
5
4
C
V
CC
GND
2
5
V
CC
Y
A
3
4
Y
001aae000
Transparent top view
Figure 2. Pin configuration SOT363 (SC-88)
74AUP1G97
B
GND
A
1
2
3
6
5
4
C
V
CC
Y
Figure 3. Pin configuration SOT886 (XSON6)
74AUP1G97
B
1
GND
3
A
2
5
4
Y
C
6
V
CC
001aae001
Transparent top view
aaa-019827
Figure 4. Pin configuration SOT891, SOT1115 and
SOT1202 (XSON6)
ball A1
index area
A
Transparent top view
Figure 5. Pin configuration SOT1255 (X2SON6)
74AUP1G97UK
1
A
B
2
C
74AUP1G97UK
1
2
B
B
GND
V
CC
Y
aaa-026279
C
aaa-026278
C
A
Transparent top view
Transparent top view
Figure 6. Pin configuration SOT1454-1 (WLCSP6)
74AUP1G97
Figure 7. Ball mapping for SOT1454-1 (WLCSP6)
© Nexperia B.V. 2017. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 10 — 28 March 2017
3 / 25
Nexperia
Low-power configurable multiple function gate
74AUP1G97
6.2 Pin description
Table 3. Pin description
Symbol
B
GND
A
Y
V
CC
C
Pin
SC88, XSON6 and X2SON6
1
2
3
4
5
6
Description
WLCSP6
A1
B1
C1
C2
B2
A2
data input
ground (0 V)
data input
data output
supply voltage
data input
7
Logic configurations
Figure
see
Figure 8
see
Figure 9
see
Figure 10
see
Figure 10
see
Figure 11
see
Figure 11
see
Figure 12
see
Figure 13
see
Figure 14
Table 4. Function selection table
Logic function
2-input MUX
2-input AND
2-input OR with one input inverted
2-input NAND with one input inverted
2-input AND with one input inverted
2-input NOR with one input inverted
2-input OR
Inverter
Buffer
V
CC
B
A
C
B
Y
A
1
2
3
6
5
4
Y
001aae002
V
CC
1
A
C
Y
A
2
3
6
5
4
Y
001aae003
C
C
Figure 8. 2-input MUX
Figure 9. 2-input AND gate
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 10 — 28 March 2017
4 / 25
Nexperia
Low-power configurable multiple function gate
V
CC
A
C
A
C
B
C
B
C
V
CC
74AUP1G97
Y
1
2
6
5
4
C
Y
B
1
2
6
5
4
C
Y
A
3
Y
001aae004
Y
3
Y
001aae005
Figure 10. 2-input NAND gate with input A inverted or 2-
input OR gate with input C inverted
V
CC
B
B
C
Y
1
2
3
6
5
4
Y
001aae006
Figure 11. 2-input NOR gate with input B inverted or 2-
input AND gate with input C inverted
V
CC
C
1
C
Y
2
3
6
5
4
C
Y
001aae007
Figure 12. 2-input OR gate
Figure 13. Inverter
V
CC
B
B
Y
1
2
3
6
5
4
Y
001aae008
Figure 14. Buffer
8
Functional description
[1]
Table 5. Function table
Input
C
L
L
L
L
H
H
H
H
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
L
H
H
L
H
L
H
H = HIGH voltage level; L = LOW voltage level.
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 10 — 28 March 2017
5 / 25
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