HT49RV9/HT49CV9
A/D With VFD Type 8-Bit MCU
Technical Document
·
Tools Information
·
FAQs
·
Application Note
-
HA0077E HT49CVX Remote Control Receiver SWIP Design Note
-
HA0078E HT49CVX Display SWIP Design Note
Features
·
Operating voltage:
·
8-bit prescaler for RTC
·
Watchdog Timer
·
Buzzer output
·
On-chip crystal, RC and 32768Hz crystal oscillator
·
HALT function and wake-up feature reduce power
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
·
32 bidirectional I/O lines (PA, PB, PC, PD)
·
Two external interrupt inputs
·
Two 16-bit programmable timer/event counters with
consumption
·
16-level subroutine nesting
·
8-channel 10-bit resolution A/D converter
·
4-channel 8-bit PWM output shared with 4 I/O lines
·
LVR function with enable/disable function
·
Bit manipulation instruction
·
16-bit table read instruction
·
Up to 0.5ms instruction cycle with 8MHz system clock
·
63 powerful instructions
·
All instructions in 1 or 2 machine cycles
·
100-pin QFP package
PFD (programmable frequency divider) function
·
One 8-bit Remote Control Timer (RMT)
·
Single channel serial interface
·
VFD driver with 12´16 segments
(12-segment & 16-grid to 20-segment & 8-grid)
·
8K´16´2 program memory
·
192´8´4 data memory RAM
·
Supports PFD for sound generation
·
Real Time Clock (RTC), 32768Hz with quick start-up
control bit
General Description
The HT49RV9/HT49CV9 are 8-bit high performance
single chip MCUs. Their single cycle instruction and
2-stage pipeline architecture make them suitable for
high speed applications. As the devices include an VFD
driver they are suitable for use in products which require
a front panel for their operation such as DVDs, VCDs,
Mini-component audio systems, cassette decks, tuners,
CD players, other home appliances, etc.
Rev. 1.00
1
April 20, 2006
HT49RV9/HT49CV9
Block Diagram
In te rru p t
C ir c u it
P ro g ra m
R O M
P ro g ra m
C o u n te r
S ta c k
IN T C
T M R 0 C
T M R 0
P F D 0
T M R 1 C
T M R 1
P F D 1
M
M
U
P r e s c a le r
X
P D 6 /T M R 0
P D 7 /T M R 1
U
X
f
S
Y S
f
S
Y S
/4
3 2 7 6 8 H z
f
S
M
U
X
/4
O S C 3
O S C 4
In s tr u c tio n
R e g is te r
M P
M
U
R T C
X
D a ta
M e m o ry
W D T
T im e B a s e
Y S
R T C O S C
W D T O S C
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e r a tio n
M U X
P W
P D C
S T A T U S
P D
P C C
P C
B P
M
P o rt D
S h ifte r
P o rt C
P D
P D
P D
P D
P D
0 /
4 /
5 /
6 /
7 /
P W
IN
IN
T M
T M
M 0 ~ P D 3 /P W
T 0
T 1
R 0
R 1
M 3
P C 0 ~ P C 7
O S C 2
O S C 4
O S
R E
V D
V S
O S
S
D
S
C 1
A C C
V F D
M e m o ry
V F D D r iv e r
8 -C h a n n e l
A /D C o n v e rte r
P B C
P B
P o rt B
P B 0 /A N 0 ~ P B 7 /A N 7
P A 0
P A 1
P A 2
P A 3
P A 4
/B Z
/B Z
/P F D
~ P A 7
C 3
P A C
V E E
G r id 0 ~
G r id 7
S E G 0 ~
S E G 1 1
S E G 1 2 /G r id 1 5 ~
S E G 1 9 /G r id 8
P A
H A L T
P o rt A
E N /D IS
L V R
H A L T
E N /D IS
S D I
S D O
S C K
S C S
S e r ia l
In te rfa c e
M U X
f
S
f
R
8 - B it R e m o te
C o n tr o l T im e r
Y S
/4
T C O S C
R M T
Rev. 1.00
2
April 20, 2006
HT49RV9/HT49CV9
Pin Assignment
N C
N C
N C
S C S
S C K
S D O
S D I
N C
N C
O S C 4
O S C 3
V D D
O S C 2
O S C 1
R E S
P A 0 /B Z
P A 1 /B Z
P A 2
P A 3 /P F D
P A 4
1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1
1
2
3
4
P
P
P
P
P
P
P A
P A
P B 0 .A N
P B 1 /A N
P B 2 /A N
P B 3 /A N
P B 4 /A N
P B 5 /A N
P B 6 /A N
P B 7 /A N
V S
D 0 /P W M
D 1 /P W M
D 2 /P W M
D 3 /P W M
P D 4 /IN T
P D 5 /IN T
D 6 /T M R
D 7 /T M R
P C
P C
P C
P C
V S
P A
N
N
N
N
N
C
C
C
C
5
8 0
7 9
7 8
7 7
N C
N C
G R ID
G R ID
G R ID
G R ID
G R ID
G R ID
G R ID
G R ID
V D D
V E E
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
N C
N C
N C
N C
N C
N C
N C
N C
N C
S E G
0
1
2
3
4
5
6
7
1 9 /G
1 8 /G
1 7 /G
1 6 /G
1 5 /G
1 4 /G
1 3 /G
1 2 /G
R ID
R ID
R ID
R ID
R ID
R ID
R ID
R ID
9
8
1 0
1 1
1 2
1 3
1 4
1 5
5
C
7
0
1
2
3
4
5
6
S
0
1
2
3
7
6
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
H T 4 9 R V 9 /H T 4 9 C V 9
1 0 0 Q F P -A
0
0
1
2
3
1
0
1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
S
5 1
1 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
N C
N C
N C
R M T
7
8
0
1
2
3
4
5
6
7
9
1 0
P C
P C
P C
P C
N C
4
5
6
Note:
Each V
DD
(V
SS
) pins must be connected to the power (ground) of the system.
Pin Description
Pin Name
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7
I/O
Options
Wake-up
Pull-high
Buzzer
PFD
Description
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by configuration option. Software instructions determine if
the pin is a CMOS output or Schmitt trigger input with or without pull-high
resistor (determined by pull-high options: bit option). Pins PA0, PA1 and
PA3 are pin-shared with BZ, BZ and PFD, respectively.
Bidirectional 8-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt trigger input with or without pull-high
resistor (determined by pull-high option: bit option) or A/D input. Once a
PB line is selected as an A/D input (by using software control), the I/O
function and pull-high resistor are disabled automatically.
Bidirectional 8-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt trigger input with or without pull-high
resistor (determined by pull-high option: bit option).
Bidirectional 4-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt trigger input with or without pull-high
resistor (determined by pull-high option: bit option).
I/O
PB0/AN0~
PB7/AN7
I/O
Pull-high
PC0~PC7
PD0/PWM0
PD1/PWM1
PD2/PWM2
PD3/PWM3
I/O
Pull-high
I/O
Pull-high
PWM
Rev. 1.00
3
April 20, 2006
HT49RV9/HT49CV9
Pin Name
PD4/INT0
PD5/INT1
PD6/TMR0
PD7/TMR1
I/O
Options
Description
Bidirectional 4-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt trigger input with or without pull-high
resistor (determined by pull-high option: bit option). Pins PD4~PD7 are
pin-shared with INT0, INT1, TMR0 & TMR1, respectively (determined by
software control).
RMT with wake-up function (both rising and falling edge) and Schmitt
trigger input with or without pull-high resistor (determined by pull-high
option).
Negative power supply, ground
VFD negative power supply
High-voltage segment output for VFD panel.
High-voltage output for VFD panel. These pins are selectable for seg-
ment or grid output.
High-voltage grid output for VFD panel.
Serial interface serial data input
Serial interface serial data output
Serial interface serial clock input/output (initial
²input²)
Serial interface chip select pin, output for master mode, input for slave
mode.
Real time clock oscillators. OSC3 and OSC4 are connected to a
32768Hz crystal oscillator for timing purposes or to a system clock
source (depending on the options). No built-in capacitor
Positive power supply
OSC1 and OSC2 are connected to an RC network or a crystal (by op-
tions) for the internal system clock. For RC operation, OSC2 is an output
pin for 1/4 system clock. The system clock may come from the RTC os-
cillator. If the system clock comes from RTCOSC, these two pins can be
left floating.
Schmitt trigger reset input, active low
I/O
Pull-high
RMT
VSS
VEE
SEG0~SEG11
SEG12/GRID15~
SEG19/GRID8
GRID0~GRID7
SDI
SDO
SCK
SCS
OSC4
OSC3
VDD
I
¾
¾
O
O
O
I
O
I/O
I/O
O
I
¾
Pull-high
¾
¾
¾
¾
¾
¾
¾
¾
¾
RTC or
System Clock
¾
OSC2
OSC1
O
I
Crystal or RC
RES
I
¾
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V
to V
SS
+6.0V
Input Voltage..............................V
SS
-0.3V
to V
DD
+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Rev. 1.00
4
April 20, 2006
HT49RV9/HT49CV9
D.C. Characteristics
Test Conditions
Symbol
Parameter
V
DD
V
DD
VEE
I
DD1
Operating Voltage
VFD Supply Voltage
Operating Current (Crystal OSC)
5V
I
DD2
3V
Operating Current (RC OSC)
5V
I
DD3
Operating Current
(f
SYS
=32768Hz)
Operating Current (Crystal OSC)
5V
I
STB1
Standby Current (*f
S
=T1)
Standby Current
(*f
S
=32768Hz OSC)
Input Low Voltage for I/O Ports,
TMR and INT
Input High Voltage for I/O Ports,
TMR and INT
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset Voltage
I/O Port Segment Logic Output
Sink Current
I/O Port Segment Logic Output
Source Current
Segment/Grid Source Current
Pull-high Resistance of I/O Ports
and INT0, INT1, RMT
A/D Input Voltage
A/D Conversion Integral
Nonlinearity Error
Additional Power Consumption
if A/D Converter is Used
²*f
S
²
Refer to WDT clock option
3V
5V
I
STB2
3V
5V
¾
¾
¾
¾
¾
3V
5V
3V
5V
5V
3V
5V
¾
¾
3V
5V
V
OH
=V
DD
-2V
¾
¾
¾
¾
¾
V
OH
=0.9V
DD
3V
5V
3V
¾
¾
¾
3V
Conditions
f
SYS
=4MHz
f
SYS
=8MHz
¾
No load, ADC off
VFD off, f
SYS
=4MHz
No load, ADC off
VFD off, f
SYS
=4MHz
No load, ADC off
VFD off
No load, ADC off
VFD on, , f
SYS
=4MHz
No load, system HALT
VFD off at HALT
No load, system HALT
VFD off at HALT
¾
¾
¾
¾
LVR voltage 3.0V option
LVR voltage 3.8V option
V
OL
=0.1V
DD
2.2
3.3
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
0
0.8V
DD
0
0.9V
DD
2.7
3.5
6
10
-2
-5
-15
40
10
0
¾
¾
¾
¾
¾
¾
2
5
1.8
4.6
1.2
4
4
7
¾
¾
4
14
¾
¾
¾
¾
3.0
3.8
12
25
-4
-8
¾
60
30
¾
±0.5
1
2
5.5
5.5
V
DD
-30
3
8
2.7
7.5
2
7
6
15
1
2
10
20
0.2V
DD
V
DD
0.4V
DD
V
DD
3.3
4.0
¾
¾
¾
¾
¾
80
50
V
DD
±1
2
4
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
mA
mA
mA
mA
mA
kW
kW
V
LSB
mA
mA
Min.
Typ.
Max.
Unit
Ta=25°C
I
DD4
V
IL1
V
IH1
V
IL2
V
IH2
V
LVR
I
OL
I
OH1
I
OH2
R
PH
V
AD
E
AD
I
ADC
Note:
Rev. 1.00
5
April 20, 2006
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