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FLEX10KA

Description
Embedded Programmable Logic Family
File Size805KB,114 Pages
ManufacturerAltera (Intel)
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FLEX10KA Overview

Embedded Programmable Logic Family

FLEX 10K
®
Embedded Programmable
Logic Family
Data Sheet
May 1998, ver. 3.10
Features...
s
s
s
The industryÕs first embedded programmable logic device (PLD)
family, providing system integration in a single device
Ð
Embedded array for implementing megafunctions, such as
efficient memory and specialized logic functions
Ð
Logic array for general logic functions
High density
Ð
10,000 to 250,000 typical gates (see Tables 1 and 2)
Ð
Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic capacity
System-level features
Ð
MultiVolt
ª
I/O interface support
Ð
5.0-V tolerant input pins in FLEX
¨
10KA devices
Ð
Low power consumption (typical specification less than 0.5 mA
in standby mode for most devices)
Ð
FLEX 10K and FLEX 10KA devices support peripheral
component interconnect Special Interest GroupÕs (PCI-SIG)
PCI
Local Bus Specification, Revision 2.1
Ð
FLEX 10KA devices include pull-up clamping diode, selectable
on a pin-by-pin basis for 3.3-V PCI compliance
Ð
Built-in JTAG boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990, available without consuming any device
logic
Table 1. FLEX 10K Device Features
Feature
Typical gates (logic and RAM),
Note (1)
Usable gates
Logic elements (LEs)
Logic array blocks (LABs)
Embedded array blocks (EABs)
Total RAM bits
Maximum user I/O pins
EPF10K10
EPF10K10A
10,000
7,000 to
31,000
576
72
3
6,144
134
EPF10K20
20,000
15,000 to
63,000
1,152
144
6
12,288
189
EPF10K30
EPF10K30A
30,000
22,000 to
69,000
1,728
216
6
12,288
246
EPF10K40
40,000
29,000 to
93,000
2,304
288
8
16,384
189
EPF10K50
EPF10K50V
50,000
36,000 to
116,000
2,880
360
10
20,480
310
Altera Corporation
A-DS-F10K-03.10
1

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