AT91SAM9263-CU datasheet, PDF - EEWORLD Datasheet

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AT91SAM9263-CU: DescriptionMicroprocessors - MPU 96kB SRAM 240MHz 4 PWM; CategoryThe embedded processor and controller Microcontrollers and processors; File Size564KB，52 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT91SAM9263-CU Overview

Microprocessors - MPU 96kB SRAM 240MHz 4 PWM

AT91SAM9263-CU Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	BGA
package instruction	TFBGA, BGA324,18X18,32
Contacts	324
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Samacsys Description	Microprocessadores - MPU 96kB SRAM 240MHz 4 PWM
Has ADC	NO
Other features	ALSO REQUIRES 3.3V SUPPLY
Address bus width	26
bit size	32
CPU series	ARM9
maximum clock frequency	50 MHz
DAC channel	NO
DMA channel	YES
External data bus width	32
JESD-30 code	S-PBGA-B324
length	15 mm
Number of I/O lines	160
Number of terminals	324
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA324,18X18,32
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
power supply	1.2,1.8,3.3 V
Certification status	Not Qualified
RAM (bytes)	98304
rom(word)	131072
ROM programmability	FLASH
Maximum seat height	1.2 mm
speed	240 MHz
Maximum supply voltage	1.32 V
Minimum supply voltage	1.08 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	15 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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Features

•

Incorporates the ARM926EJ-S

™

ARM

Thumb

Processor

– DSP Instruction Extensions, Jazelle

Technology for Java

Acceleration

– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer

– 220 MIPS at 200 MHz

– Memory Management Unit

– EmbeddedICE

™

, Debug Communication Channel Support

– Mid-level Implementation Embedded Trace Macrocell

™

Bus Matrix

– Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth

– Boot Mode Select Option, Remap Command

Embedded Memories

– One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed

– One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus

Matrix Speed

– One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed

Dual External Bus Interface (EBI0 and EBI1)

– EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and

CompactFlash

– EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash

DMA Controller (DMAC)

– Acts as one Bus Matrix Master

– Embeds 2 Unidirectional Channels with Programmable Priority, Address

Generation, Channel Buffering and Control

Twenty Peripheral DMA Controller Channels (PDC)

LCD Controller

– Supports Passive or Active Displays

– Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode

– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual

Screen Buffers

Two D Graphics Accelerator

– Line Draw, Block Transfer, Clipping, Commands Queuing

Image Sensor Interface

– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate

– 12-bit Data Interface for Support of High Sensibility Sensors

– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format

USB 2.0 Full Speed (12 Mbits per second) Host Double Port

– Dual On-chip Transceivers

– Integrated FIFOs and Dedicated DMA Channels

USB 2.0 Full Speed (12 Mbits per second) Device Port

– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM

Ethernet MAC 10/100 Base-T

– Media Independent Interface or Reduced Media Independent Interface

– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit

Fully-featured System Controller, including

– Reset Controller, Shutdown Controller

– Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes

– Clock Generator and Power Management Controller

– Advanced Interrupt Controller and Debug Unit

– Periodic Interval Timer, Watchdog Timer and Double Real-time Timer

•

AT91 ARM

Thumb

Microcontrollers

AT91SAM9263

•

Summary

•

NOTE:

This is a summary document.

The complete document is available on

the Atmel website at www.atmel.com.

6249HS–ATARM–27-Jul-09

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