LP38692SD-5.0 datasheet, PDF - EEWORLD Datasheet

LP38692SD-5.0: DescriptionLDO Voltage Regulators 1A Low Dropout CMOS Linear Regulators, Stable with Ceramic Output Capacitors 6-WSON -40 to 125; CategoryPower/power management The power supply circuit; File Size2MB，33 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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LP38692SD-5.0 Overview

LDO Voltage Regulators 1A Low Dropout CMOS Linear Regulators, Stable with Ceramic Output Capacitors 6-WSON -40 to 125

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Texas Instruments
Parts packaging code	SOIC
package instruction	HVSON, SOLCC6,.13,38
Contacts	6
Reach Compliance Code	not_compliant
ECCN code	EAR99
Samacsys Description	IC REG LDO 1A 5.0V
Adjustability	FIXED
Maximum drop-back voltage 1	0.8 V
Nominal dropback voltage 1	0.45 V
Maximum absolute input voltage	12 V
Maximum input voltage	10 V
Minimum input voltage	2.7 V
JESD-30 code	S-PDSO-N6
JESD-609 code	e0
length	3 mm
Maximum grid adjustment rate	0.0225%
Maximum load regulation	0.24975%
Humidity sensitivity level	1
Number of functions	1
Output times	1
Number of terminals	6
Working temperatureTJ-Max	125 °C
Working temperature TJ-Min	-40 °C
Maximum output current 1	1 A
Maximum output voltage 1	5.25 V
Minimum output voltage 1	4.75 V
Nominal output voltage 1	5 V
Package body material	PLASTIC/EPOXY
encapsulated code	HVSON
Encapsulate equivalent code	SOLCC6,.13,38
Package shape	SQUARE
Package form	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Regulator type	FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
Maximum seat height	0.8 mm
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD
Terminal pitch	0.95 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Maximum voltage tolerance	5%
width	3 mm

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