XC5206-6PQG160C datasheet, PDF

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XC5206-6PQG160C: DescriptionField Programmable Gate Array, 196 CLBs, 6000 Gates, 83MHz, CMOS, PQFP160, PLASTIC, QFP-160; CategoryProgrammable logic devices Programmable logic; File Size670KB，73 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/; Environmental Compliance

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XC5206-6PQG160C Overview

Field Programmable Gate Array, 196 CLBs, 6000 Gates, 83MHz, CMOS, PQFP160, PLASTIC, QFP-160

XC5206-6PQG160C Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	XILINX
Parts packaging code	QFP
package instruction	QFP,
Contacts	160
Reach Compliance Code	compliant
Other features	MAX AVAILABLE 10000 LOGIC GATES
maximum clock frequency	83 MHz
Combined latency of CLB-Max	5.6 ns
JESD-30 code	S-PQFP-G160
JESD-609 code	e3
length	28 mm
Humidity sensitivity level	3
Configurable number of logic blocks	196
Equivalent number of gates	6000
Number of terminals	160
Maximum operating temperature	85 °C
Minimum operating temperature
organize	196 CLBS, 6000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	245
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	28 mm
Base Number Matches	1

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Product Obsolete or Under Obsolescence

XC5200 Series

Field Programmable Gate Arrays

November 5, 1998 (Version 5.2)

Product Specification

Footprint compatibility in common packages within

the XC5200 Series and with the XC4000 Series

- Over 150 device/package combinations, including

advanced BGA, TQ, and VQ packaging available

Fully Supported by Xilinx Development System

- Automatic place and route software

- Wide selection of PC and Workstation platforms

- Over 100 3rd-party Alliance interfaces

- Supported by shrink-wrap Foundation software

Features

• Low-cost, register/latch rich, SRAM based

reprogrammable architecture

- 0.5µm three-layer metal CMOS process technology

- 256 to 1936 logic cells (3,000 to 23,000 “gates”)

- Price competitive with Gate Arrays

• System Level Features

- System performance beyond 50 MHz

- 6 levels of interconnect hierarchy

- VersaRing

™

I/O Interface for pin-locking

- Dedicated carry logic for high-speed arithmetic

functions

- Cascade chain for wide input functions

- Built-in IEEE 1149.1 JTAG boundary scan test

circuitry on all I/O pins

- Internal 3-state bussing capability

- Four dedicated low-skew clock or signal distribution

nets

• Versatile I/O and Packaging

- Innovative VersaRing

™

I/O interface provides a high

logic cell to I/O ratio, with up to 244 I/O signals

- Programmable output slew-rate control maximizes

performance and reduces noise

- Zero Flip-Flop hold time for input registers simplifies

system timing

- Independent Output Enables for external bussing

•

Description

The XC5200 Field-Programmable Gate Array Family is

engineered to deliver low cost. Building on experiences

gained with three previous successful SRAM FPGA fami-

lies, the XC5200 family brings a robust feature set to pro-

grammable logic design. The VersaBlock

™

logic module,

the VersaRing I/O interface, and a rich hierarchy of inter-

connect resources combine to enhance design flexibility

and reduce time-to-market. Complete support for the

XC5200 family is delivered through the familiar Xilinx soft-

ware environment. The XC5200 family is fully supported on

popular workstation and PC platforms. Popular design

entry methods are fully supported, including ABEL, sche-

matic capture, VHDL, and Verilog HDL synthesis. Design-

ers utilizing logic synthesis can use their existing tools to

design with the XC5200 devices.

Table 1: XC5200 Field-Programmable Gate Array Family Members

Device

Logic Cells

Max Logic Gates

Typical Gate Range

VersaBlock Array

CLBs

Flip-Flops

I/Os

TBUFs per Longline

XC5202

256

3,000

2,000 - 3,000

8x8

256

XC5204

480

6,000

4,000 - 6,000

10 x 12

120

480

124

XC5206

784

10,000

6,000 - 10,000

14 x 14

196

784

148

XC5210

1,296

16,000

XC5215

1,936

23,000

10,000 - 16,000 15,000 - 23,000

18 x 18

324

1,296

196

22 x 22

484

1,936

244

November 5, 1998 (Version 5.2)

7-83

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