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MN4027B

Description
J-K Flip-Flop, 4000/14000/40000 Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, PLASTIC, DIP-16
Categorylogic    logic   
File Size336KB,4 Pages
ManufacturerPanasonic
Websitehttp://www.panasonic.co.jp/semicon/e-index.html
Download Datasheet Parametric Compare View All

MN4027B Overview

J-K Flip-Flop, 4000/14000/40000 Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, PLASTIC, DIP-16

MN4027B Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPanasonic
Parts packaging codeDIP
package instructionPLASTIC, DIP-16
Contacts16
Reach Compliance Codeunknown
series4000/14000/40000
JESD-30 codeR-PDIP-T16
JESD-609 codee0
Logic integrated circuit typeJ-K FLIP-FLOP
Number of digits2
Number of functions2
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5/15 V
propagation delay (tpd)345 ns
Certification statusNot Qualified
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
minfmax11 MHz
Base Number Matches1
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MN4027B Related Products

MN4027B MN4027BS
Description J-K Flip-Flop, 4000/14000/40000 Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, PLASTIC, DIP-16 J-K Flip-Flop, 4000/14000/40000 Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, SOP-16
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Maker Panasonic Panasonic
Parts packaging code DIP SOIC
package instruction PLASTIC, DIP-16 SOP-16
Contacts 16 16
Reach Compliance Code unknown unknown
series 4000/14000/40000 4000/14000/40000
JESD-30 code R-PDIP-T16 R-PDSO-G16
JESD-609 code e0 e0
Logic integrated circuit type J-K FLIP-FLOP J-K FLIP-FLOP
Number of digits 2 2
Number of functions 2 2
Number of terminals 16 16
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Output polarity COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP SOP
Encapsulate equivalent code DIP16,.3 SOP16,.25
Package shape RECTANGULAR RECTANGULAR
Package form IN-LINE SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
power supply 5/15 V 5/15 V
propagation delay (tpd) 345 ns 345 ns
Certification status Not Qualified Not Qualified
surface mount NO YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE GULL WING
Terminal pitch 2.54 mm 1.27 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
Trigger type POSITIVE EDGE POSITIVE EDGE
minfmax 11 MHz 11 MHz
Base Number Matches 1 1
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