and/or fractional divides are allowed on two of the PLLs.
There are a total of six 8-bit output dividers. Each output
bank can be configured to support LVTTL, LVPECL, LVDS
or HCSL logic levels. Out0 (Output 0) supports 3.3V
single-ended output only. The outputs are connected to the
PLLs via a switch matrix. The switch matrix allows the user
to route the PLL outputs to any output bank. This feature
can be used to simplify and optimize the board layout. In
addition, each output's slew rate and enable/disable
function is programmable.
IDT5V49EE902
Features
•
•
•
•
•
•
Four internal PLLs
Internal non-volatile EEPROM
Fast (400kHz) mode I
2
C serial interface
Input frequency range: 1 MHz to 200 MHz
Output frequency range: 4.9 kHz to 500 MHz
Reference crystal input with programmable linear load
capacitance
– Crystal frequency range: 8 MHz to 50 MHz
•
Four independently controlled VDDO (1.8V - 3.3V)
•
Each PLL has a 7-bit reference divider and a 12-bit
feedback-divider
•
8-bit output-divider blocks
•
Fractional division capability on one PLL
•
Two of the PLLs support spread spectrum generation
capability
•
I/O Standards:
– Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS
– Outputs - LVPECL, LVDS and HCSL
– Inputs - 3.3 V LVTTL/ LVCMOS
•
•
•
•
•
•
•
•
•
Programmable slew rate control
Programmable loop bandwidth
Programmable output inversion to reduce bimodal jitter
Redundant clock inputs with auto and manual switchover
options
Individual output enable/disable
Power-down mode
3.3V core V
DD
Available in VFQFPN package
-40 to +85 C Industrial Temp operation
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
1
IDT5V49EE902
REV Q 071015
IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Functional Block Diagram
S
R
C
0
S
R
C
1
S
R
C
2
S
R
C
4
S
R
C
3
S
R
C
6
Control
Logic
S
R
C
5
S1
OUT0
XIN/REF
XOUT
PLL0 (SS)
/DIV1
OUT1
CLKIN
PLL1
/DIV2
OUT2
CLKSEL
PLL2
OUT4
/DIV4
OUT4
S3
PLL3 (SS)
/DIV3
OUT3
SD/OE
SDA
SCL
SEL[2:0]
/DIV6
OUT6
OUT5
/DIV5
OUT5
1. OUT1 & OUT2, OUT4 & OUT4, OUT3 & OUT6, and OUT5 & OUT5 pairs can be
configured to be LVDS, LVPECL or HCSL, or two single-ended LVTTL outputs.
2. CLKIN, CLKSEL, SD/OE and SEL[2:0] have pull down resistors.
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
2
IDT5V49EE902
REV Q 071015
IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
PIN CONFIGURATION
VDDO3
SD/OE
OUT0
SEL1
SEL2
SEL0
.
GND
31
VDD
32
29
28
27
26
25
30
VDD
XOUT
XIN/REF
VDDx
CLKIN
GND
OUT1
OUT2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
OUT3
OUT6
GND
AVDD
CLKSEL
SCLK
SDAT
GND
12
10
OUT4
11
13
14
15
16
Pin Descriptions
Pin Name
CLKIN
XOUT
XIN / REF
SDAT
9
VDDO1
OUT5b
OUT5
32 pin VFQFPN
(Top View)
OUT4b
NL32
Pin#
5
2
3
18
VDDO4
GND
VDDO5
I/O
I
O
I
I/O
Pin Type
LVTTL
LVTTL
LVTTL
Open Drain
Pin Description
Input clock. Weak internal pull down resistor.
CRYSTAL_OUT -- Reference crystal feedback.
CRYSTAL_IN -- Reference crystal input or external
reference clock input.
Bidirectional I
2
C data. An external pull-up resistor is
required. See I
2
C specification for pull-up value
recommendation.
I
2
C clock. An external pull-up resistor is required. See
I
2
C specification for pull-up value recommendation.
Input clock selector. Weak internal pull down resistor.
Configuration select pin. Weak internal pull down
resistor.
Configuration select pin. Weak internal pull down
resistor.
Configuration select pin. Weak internal pull down
resistor.
Enables/disables the outputs or powers down the chip.
The SP bit (0x02) controls the polarity of the signal to be
either active HIGH or LOW. (Default is active LOW.)
Weak internal pull down resistor.
Configurable clock output 0. 3.3V LVTTL levels.
SCLK
CLKSEL
SEL2
SEL1
SEL0
SD/OE
19
20
26
27
28
29
I
I
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
OUT0
30
O
LVTTL
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
3
IDT5V49EE902
REV Q 071015
IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin Name
OUT1
NL32
Pin#
7
I/O
O
Pin Type
Adjustable
1
Pin Description
Configurable clock output 1. Single-ended or differential
when combined with OUT2. Output levels controlled by
VDDO1.
Configurable clock output 2. Single-ended or differential
when combined with OUT1. Output levels controlled by
VDDO1.
Configurable clock output 3. Single-ended or differential
when combined with OUT6. Output levels controlled by
VDDO3.
Configurable clock output 4. Single-ended or differential
when combined with OUT4b. Output levels controlled by
VDDO4.
Configurable clock output 4b. Single-ended or differential
when combined with OUT4. Output levels controlled by
VDDO4.
Configurable clock output 5. Single-ended or differential
when combined with OUT5b. Output levels controlled by
VDDO5.
Configurable clock output 5b. Single-ended or differential
when combined with OUT5. Output levels controlled by
VDDO5.
Configurable clock output 6. Single-ended or differential
when combined with OUT3. Output levels controlled by
VDDO3.
Device power supply. Connect to 3.3V.
Crystal oscillator power supply. Connect to 3.3V through
5 resistor. Use filtered analog power supply if available.
Device analog power supply. Connect to 3.3V. Use
filtered analog power supply if available.
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT1 and OUT2.
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT3 and OUT6.
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT4 and OUT4b.
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT5 and OUT5b.
Connect to Ground.
OUT2
8
O
Adjustable
1
OUT3
24
O
Adjustable
1
OUT4
10
O
Adjustable
1,2
OUT4b
11
O
Adjustable
1,2
OUT5
14
O
Adjustable
1,2
OUT5b
15
O
Adjustable
1,2
OUT6
23
O
Adjustable
1
VDD
VDDx
AVDD
VDDO1
VDDO3
VDDO4
VDDO5
GND
1,4, 21,
32
4
21
9
25
12
16
6, 13,
17, 22,
31,PAD
Power
Power
Power
Power
Power
Power
Power
Power
1.Outputs are user programmable to drive single-ended 3.3-V LVTTL, or differential LVDS, LVPECL or HCSL interface levels
2. When only an individual single-ended clock output is required, tie OUT# and OUT#b together.
3. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.
4. Each power pin should have a dedicated 0.01µF de-coupling capacitor. Digital VDDs may be tied together.
5. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
4
IDT5V49EE902
REV Q 071015
IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
PLL Features and Descriptions
7-bit
D
VCO
4-bit
A
12-bit
N
Sigm a-Delta
M odulator
PLL0 Block Diagram
7-bit
D
VCO
12-bit
N
PLL1, PLL2 and PLL3 Block Diagram
Pre-Divider
(D)
1
Values
PLL0
PLL1
PLL2
PLL3
1 - 127
1 - 127
1 - 127
3 - 127
Multiplier
(M)
2
Values
10 - 8206
1 - 4095
1 - 4095
12 - 4095
Programmable
Spread Spectrum
Loop Bandwidth Generation Capability
Yes
Yes
Yes
Yes
Yes
No
No
Yes
1.For PLL0, PLL1 and PLL2, D=0 means PLL power down. For PLL3, 0, 1, and 2 are DNU (do not use)
2.For PLL0, M = 2*N + A + 1 (for A > 0); M = 2*N (for A = 0); A < N-1. For PLL1, PLL2 and PLL3, M=N.
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Analogue and Mixed Signal
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