Integrated
Circuit
Systems, Inc.
ICS9DB401
Four Output Differential Buffer for PCI Express
Recommended Application:
DB800 Version 2.0 Yellow Cover part with PCI Express
support with extended bypass mode frequency range.
Output Features:
•
4 - 0.7V current-mode differential output pairs
•
Supports zero delay buffer mode and fanout mode
•
Bandwidth programming available
Key Specifications:
•
Outputs cycle-cycle jitter: < 50ps
•
Outputs skew: < 50ps
•
Extended frequency range in bypass mode:
Revision B: up to 333.33MHz
Revision C: up to 400MHz
Features/Benefits:
•
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
•
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Pin Configurations
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
OE_INV
VDD
DIF_6
DIF_6#
OE_6
DIF_5
DIF_5#
VDD
HIGH_BW#
SRC_STOP#
PD#
OE_INV = 0
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
OE_INV
VDD
DIF_6
DIF_6#
OE6#
DIF_5
DIF_5#
VDD
HIGH_BW#
SRC_STOP
PD
OE_INV = 1
28-pin SSOP & TSSOP
1014B—09/07/06
ICS9DB401
ICS9DB401
(same as ICS9DB104)
Integrated
Circuit
Systems, Inc.
ICS9DB401
Pin Decription When OE_INV = 0
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN NAME
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
PD#
SRC_STOP#
HIGH_BW#
VDD
DIF_5#
DIF_5
OE_6
DIF_6#
DIF_6
VDD
OE_INV
PIN TYPE
PWR
IN
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
IN
I/O
IN
IN
IN
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
Active low input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
26
27
28
IREF
GNDA
VDDA
OUT
PWR
PWR
1014B—09/07/06
2
Integrated
Circuit
Systems, Inc.
ICS9DB401
Pin Decription When OE_INV = 1
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN NAME
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
PD
SRC_STOP
HIGH_BW#
VDD
DIF_5#
DIF_5
OE6#
DIF_6#
DIF_6
VDD
OE_INV
PIN TYPE
PWR
IN
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
IN
I/O
IN
IN
IN
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active high input pin used to power down the device. The
internal clocks are disabled and the VCO is stopped.
Active high input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
26
27
28
IREF
GNDA
VDDA
OUT
PWR
PWR
1014B—09/07/06
3
Integrated
Circuit
Systems, Inc.
ICS9DB401
General Description
The
ICS9DB401
follows the Intel DB400 Differential Buffer Specification v2.0. This buffer provides four PCI-Express SRC
clocks. The
ICS9DB401
is driven by a differential input pair from a CK409/CK410/CK410M main clock generator, such as the
ICS952601, ICS954101 or ICS954201. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew
(50ps) requirements.
Block Diagram
4
OE(3:0)
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
4
STOP
LOGIC
DIF(3:0))
PD
BYPASS#/PLL
SDATA
SCLK
CONTROL
LOGIC
IREF
Note: Polarities shown for OE_INV = 0.
Power Groups
Pin Number
VDD
GND
1
4
5,11,18, 24
4
N/A
27
28
27
Description
SRC_IN/SRC_IN#
DIF(1,2,5,6)
IREF
Analog VDD & GND for PLL core
1014B—09/07/06
4
Integrated
Circuit
Systems, Inc.
ICS9DB401
Absolute Max
Symbol
VDD_A
VDD_In
V
IL
V
IH
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
Max
4.6
4.6
V
DD
+0.5V
-65
0
150
70
115
Units
V
V
V
V
C
°C
°C
V
°
GND-0.5
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
Operating Supply Current
Powerdown Current
Input Frequency
Input Frequency
Input Frequency
Pin Inductance
1
1
CONDITIONS
MIN
3.3 V +/-5%
2
GND - 0.3
3.3 V +/-5%
V
IN
= V
DD
-5
V
IN
= 0 V; Inputs with no pull-up
-5
resistors
V
IN
= 0 V; Inputs with pull-up
-200
resistors
Full Active, C
L
= Full load;
all diff pairs driven
all differential pairs tri-stated
PLL Mode
Bypass Mode (Revision B/REV
ID = 1H)
Bypass Mode (Revision C/REV
ID = 2H)
Logic Inputs
Output pin capacitance
PLL Bandwidth when
PLL_BW=0
PLL Bandwidth when
PLL_BW=1
From V
DD
Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
TYP
MAX
UNITS NOTES
V
DD
+ 0.3
V
0.8
V
5
uA
uA
uA
I
DD3.3PLL
I
DD3.3ByPass
I
DD3.3PD
F
iPLL
F
iBypass
F
iBypass
L
pin
C
IN
C
OUT
BW
175
160
50
0
0
1.5
2.4
0.7
3
1
200
175
40
4
200
333.33
400
7
4
4
3.4
1.4
mA
mA
mA
mA
MHz
MHz
MHz
nH
pF
pF
MHz
MHz
1
1
1
1
1
Input Capacitance
PLL Bandwidth
Clk Stabilization
1,2
T
STAB
fMOD
0.5
30
10
1
33
15
300
5
5
ms
kHz
ns
us
ns
ns
1,2
1
1,3
1,3
1
2
Triangular Modulation
DIF output enable after
Tdrive_SRC_STOP#
SRC_Stop# de-assertion
DIF output enable after
Tdrive_PD#
PD# de-assertion
Fall time of PD# and
Tfall
SRC_STOP#
Rise time of PD# and
Trise
SRC_STOP#
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Time from deassertion until outputs are >200 mV
Modulation Frequency
1014B—09/07/06
5
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