Integrated
Circuit
Systems, Inc.
ICS8431-21
350MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Fully integrated PLL
•
Differential 3.3V LVPECL output
•
Crystal oscillator interface
•
Output frequency range: 62.5MHz to 350MHz
•
Crystal input frequency range: 14MHz to 25MHz
•
VCO range: 250MHz to 700MHz
•
Programmable PLL loop divider for generating a variety
of output frequencies
•
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI
•
PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
•
Cycle-to-cycle jitter: 30ps (maximum)
•
3.3V supply voltage
•
0°C to 85°C ambient operating temperature
•
Replaces ICS8431-01 and ICS8431-11
•
Lead-Free package fully RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS8431-21 is a general purpose clock fre-
quency synthesizer for IA64/32 application and a
HiPerClockS™
member of the HiPerClockS™ family of High Per-
formance Clock Solutions from ICS. The VCO op-
erates at a frequency range of 250MHz to 700MHz
providing an output frequency range of 62.5MHz to 350MHz.
The output frequency can be programmed using the parallel in-
terface, M0 through M8 to the configuration logic, and the output
divider control pin, DIV_SEL. Spread spectrum clocking is pro-
grammed via the control inputs SSC_CTL0 and SSC_CTL1.
ICS
Programmable features of the ICS8431-21 support four op-
erational modes. The four modes are spread spectrum clock-
ing (SSC), non-spread spectrum clock and two test modes
which are controlled by the SSC_CTL[1:0] pins. Unlike other
synthesizers, the ICS8431-21 can immediately change
spread-spectrum operation without having to reset the device.
In SSC mode, the output clock is modulated in order to achieve
a reduction in EMI. In one of the PLL bypass test modes, the
PLL is disconnected as the source to the differential output
allowing an external source to be connected to the TEST_I/O
pin. This is useful for in-circuit testing and allows the differen-
tial output to be driven at a lower frequency throughout the
system clock tree. In the other PLL bypass mode, the oscilla-
tor divider is used as the source to both the M and the Fout
divide by 2. This is useful for characterizing the oscillator and
internal dividers.
B
LOCK
D
IAGRAM
XTAL_IN
OSC
XTAL_OUT
÷
16
P
IN
A
SSIGNMENT
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
V
EE
TEST_I/O
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
V
CC
XTAL_IN
XTAL_OUT
nc
nc
V
CCA
V
EE
MR
DIV_SEL
V
CCO
FOUT
nFOUT
V
EE
PLL
PHASE
DETECTOR
÷2
VCO
÷
M
÷4
FOUT
nFOUT
ICS8431-21
TEST_I/O
Configuration
Logic
SSC
Control
Logic
M0:M8
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
M Package
Top View
nP_LOAD
SSC_CTL0
SSC_CTL1
DIV_SEL
8431AM-21
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 27, 2005
Integrated
Circuit
Systems, Inc.
ICS8431-21
350MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
The PLL loop divider or M divider is programmed by using
inputs M0 through M8. While the nP_LOAD input is held LOW,
the data present at M0:M8 is transparent to the M divider. On
the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is
latched into the M divider and any further changes at the
M0:M8 inputs will not be seen by the M divider until the next
LOW transition on nP_LOAD.
The relationship between the VCO frequency, the crystal fre-
quency and the M divider is defined as follows:
fxtal x
fVCO =
M
16
The M value and the required values of M0:M8 for programming
the VCO are shown in
Table 3B,
Programmable VCO Frequency
Function Table. The frequency out is defined as follows:
FOUT = fVCO = fxtal x M
N
16 x N
For the ICS8431-21, the output divider may be set to either
÷2
or
÷4
by the DIV_SEL pin. For an input of 16 MHz, valid
M values for which the PLL will achieve lock are defined as:
250
≤
M
≤
511.
F
UNCTIONAL
D
ESCRIPTION
The ICS8431-21 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
The output of the oscillator is divided by 16 prior to the phase
detector. With a 16MHz crystal this provides a 1MHz reference
frequency. The VCO of the PLL operates over a range of 250MHz
to 700MHz. The output of the M divider is also applied to the phase
detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (ei-
ther too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
the LVPECL output buffer. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8431-21 support four
output operational modes and a programmable M divider and
output divider. The four output operational modes are spread
spectrum clocking (SSC), non-spread spectrum clock and
two test modes and are controlled by the SSC_CTL[1:0] pins.
8431AM-21
www.icst.com/products/hiperclocks.html
2
REV. A APRIL 27, 2005
Integrated
Circuit
Systems, Inc.
ICS8431-21
350MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Type
Input
Input
Input
Power
Input /
Output
Power
Output
Power
Input
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 4,
5, 6, 7
8, 9
10, 11
12, 15, 21
13
14, 27
16, 17
18
19
Name
M0-M6
M7-M8
SSC CTL0,
SSC CTL1
V
EE
TEST I/O
V
CC
nFOUT, FOUT
V
CCO
DIV_SEL
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL pins interface levels.
Pullup
Pullup
SCC control pins. LVTTL / LVCMOS interface levels.
Negative supply pins. Connect all V
EE
pins to board ground.
Programmed as defined in Table 3A Function Table.
Core supply pin.
Differential outputs for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
Determines the output divide value for FOUT.
Pulldown
LVCMOS / LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true output FOUT to go low and the inver ted output
Pulldown nFOUT to go high. When logic LOW, the internal dividers and the
outputs are enabled. Asser tion of MR does not effect loaded M and T
values. LVCMOS / LVTTL interface levels.
Analog supply pin.
20
MR
Input
22
23, 24
V
CCA
nc
XTAL_OUT,
XTAL_IN
Power
Unused
No connect.
Crystal oscillator interface. XTAL_IN is the input.
25, 26
Input
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0
28
nP_LOAD
Input
Pulldown
is loaded into M divider. LVTTL / LVCMOS interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Pin Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
8431AM-21
www.icst.com/products/hiperclocks.html
3
REV. A APRIL 27, 2005
Integrated
Circuit
Systems, Inc.
ICS8431-21
350MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Outputs
SSC
FOUT, nFOUT
DIV_SEL0 DIV_SEL1
fXTAL
÷
32
fXTAL x M
32
Test Clk
fXTAL
÷
64
fXTAL x M
64
Test Clk
fXTAL x M
64
TEST_I/O
Operational Modes
T
ABLE
3A. SSC C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SSC_CTL1 SSC_CTL0
0
0
1
1
0
1
0
1
TEST_I/O
Source
Internal
PLL
External
PLL
Disabled
Enabled
Disabled
Disabled
fXTAL
÷
16 PLL bypass; oscillator, M and N
÷
M
dividers test mode. NOTE 1
Default SSC;
Hi-Z
Modulation Factor = ½ Percent
PLL Bypass Mode, NOTE 1;
Input
(1MHz
≤
Test Clk
≤
200MHz)
Hi-Z
No SSC Modulation
fXTAL x M
32
NOTE 1: Used for in house debug and characterization.
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
VCO Frequency
(MHz)
250
251
252
253
•
•
508
509
510
511
M Count
250
25 1
25 2
253
•
•
50 8
50 9
510
511
256
M8
0
0
0
0
•
•
1
1
1
1
128
M7
1
1
1
1
•
•
1
1
1
1
64
M6
1
1
1
1
•
•
1
1
1
1
32
M5
1
1
1
1
•
•
1
1
1
1
16
M4
1
1
1
1
•
•
1
1
1
1
8
M3
1
1
1
1
•
•
1
1
1
1
4
M2
0
0
1
1
•
•
1
1
1
1
2
M1
1
1
0
0
•
•
0
0
1
1
1
M0
0
1
0
1
•
•
0
1
0
1
NOTE 1: Assumes a 16MHz cr ystal.
T
ABLE
3C. F
UNCTION
T
ABLE
Inputs
DIV_SEL
0
1
N Divider Value
2
4
Output Frequency (MHz)
Minimum
125
62.5
Maximum
350
175
8431AM-21
www.icst.com/products/hiperclocks.html
4
REV. A APRIL 27, 2005
Integrated
Circuit
Systems, Inc.
ICS8431-21
350MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
46.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
CC
V
CCO
V
CCA
I
EE
I
CCA
Parameter
Core Supply Voltage
Output Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
155
16
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
IH
Input
Parameter
M0:M8, SSC_CTL0,
SSC_CTL1, MR,
High Voltage
DIV_SEL, TEST_I/O,
nP_LOAD
M0:M8, SSC_CTL0,
SSC_CTL1, MR,
Low Voltage
DIV_SEL, TEST_I/O,
nP_LOAD
M7, M8, SSC_CTL0,
SSC_CTL1, TEST_IO
High Current
M0:M6, DIV_SEL
nP_LOAD, MR
M7, M8, SSC_CTL0,
SSC_CTL1, TEST_IO
Low Current
M0:M6, DIV_SEL
nP_LOAD, MR
Test Conditions
Minimum
2
Typical
Maximum
V
CC
+ 0.3
Units
V
V
IL
Input
-0.3
0.8
V
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
5
150
µA
µA
µA
µA
I
IH
Input
I
IL
Input
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Output terminated with 50
Ω
to V
CCO
- 2V. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
www.icst.com/products/hiperclocks.html
5
8431AM-21
REV. A APRIL 27, 2005
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