5962-0324601Q9A datasheet, PDF

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5962-0324601Q9A: DescriptionRISC Microprocessor, 32-Bit, 15MHz, CMOS, CQFP256, CERAMIC, QFP-256; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，42 Pages; Manufacturere2v technologies

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5962-0324601Q9A Overview

RISC Microprocessor, 32-Bit, 15MHz, CMOS, CQFP256, CERAMIC, QFP-256

5962-0324601Q9A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	e2v technologies
Parts packaging code	QFP
package instruction	QFF,
Contacts	256
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	30.3 MHz
External data bus width	32
Format	FLOATING POINT
Integrated cache	NO
JESD-30 code	S-CQFP-F256
length	37.085 mm
low power mode	YES
Humidity sensitivity level	1
Number of terminals	256
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	3.18 mm
speed	15 MHz
Maximum supply voltage	3.45 V
Minimum supply voltage	3.15 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	0.508 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	37.085 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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eatures

•

Integer Unit Based on SPARC V7 High-performance RISC Architecture

•

Optimized Integrated 32/64-bit Floating-point Unit

•

On-chip Peripherals

– EDAC and Parity Generator and Checker

– Memory Interface

Chip Select Generator

Waitstate Generation

Memory Protection

– DMA Arbiter

– Timers

General Purpose Timer (GPT)

Real-time Clock Timer (RTCT)

Watchdog Timer (WDT)

– Interrupt Controller With 5 External Inputs

– General Purpose Interface (GPI)

– Dual UART

Speed Optimized Code RAM Interface

8- or 40-bit boot-PROM (Flash) Interface

IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes

Fully Static Design

Performance: 12 MIPs/3 MFlops (Double Precision) at SYSCLK = 15 MHz

Core Consumption: 0.3W Typ. at 12 MIPs

Operating Range: 3.15V to 3.45V -55°C to +125°C

Tested up to a Total Dose of 300 Krds (si) according toMIL STD 883 Method 1019

No Single Event Latch-up Below an LET Threshold of 80 MeV/mg/cm

Single Event Upsets Error Rate Better than:

– 2 E-7 Error/Component/Day in GEO Orbit

– 5 E-5 Error/Component/Day in LEO Orbit (53°, 1000 km)

Quality Grades: ESCC, and QMLQ or V with 5962-03246

Package: 256 MQFPF; Bare Die

•

Low-Voltage

Rad-Hard 32-bit

SPARC

Embedded

Processor

TSC695FL

Description

The TSC695FL (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit

RISC embedded processor implementing the SPARC architecture V7 specification. It

has been developed with the support of the ESA (European Space Agency), and

offers a full development environment for embedded space applications.

The processor is manufactured using the Atmel 0.5 µm radiation tolerant (≥ 300

KRADs (Si)) CMOS enhanced process (RTP). It can operate at a low voltage for opti-

mized power consumption (see datasheet TSC695FL). It has been specially designed

for space, as it has on-chip concurrent transient and permanent error detection.

The TSC695FL includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a

Memory Controller and a DMA arbiter. For real-time applications, the TSC695FL

offers a high security watchdog, two timers, an interrupt controller, parallel and serial

interfaces. Fault tolerance is supported using parity on internal/external buses and an

EDAC on the external data bus. The design is highly testable with the support of an

On-Chip Debugger (OCD), and a boundary scan through JTAG interface.

The TSC695FL is a selection of the TSC5695F performed for a narrow 3.3V biasing

voltage range (± 0.15V), as such, this specification can be only met by the products

solds as TSC695FL. Where computing power is not the key factor, it allows for a dra-

matic power consumption reduction (70%).

Rev. 4204C–AERO–05/05

TSC695FL

roduct

escription

Integer Unit

The IU is designed for highly dependable space and military applications, and includes

support for error detection. The RISC architecture makes the creation of a processor

that can execute instructions at a rate approaching one instruction per processor clock

possible.

To achieve that rate of execution, the IU employs a four-stage instruction pipeline that

permits parallel execution of multiple instructions.

•

Fetch - The processor outputs the instruction address to fetch the instruction.

Decode - The instruction is placed in the instruction register and is decoded. The

processor reads the operands from the register file and computes the next

instruction address.

Execute - The processor executes the instruction and saves the results in temporary

registers. Pending traps are prioritized and internal traps are taken during this stage.

Write - If no trap is taken, the processor writes the result to the destination register.

•

All four stages operate in parallel, working on up to four different instructions at a time. A

basic ’single-cycle’ instruction enters the pipeline and completes in four cycles.

By the time it reaches the write stage, three more instructions have entered and are

moving through the pipeline behind it. So, after the first four cycles, a single-cycle

instruction exits the pipeline and a single-cycle instruction enters the pipeline on every

cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but

they are called single cycle because with this type of instruction the processor can com-

plete one instruction per cycle after the initial four-cycle delay.

Floating-point Unit

The FPU is designed to provide execution of single and double-precision floating-point

instructions concurrently with execution of integer instructions by the IU. The FPU is

compliant to the ANSI/IEEE-754 (1985) floating-point standard.

The FPU is designed for highly dependable space and military applications, and

includes support for concurrent error detection and testability.

The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and

write stages (F, D, E and W). The fetch unit captures instructions and their addresses

from the data and address busses. The decode unit contains logic to decode the float-

ing-point instruction opcodes. The execution unit handles all instruction execution. The

execution unit includes a floating-point queue (FP queue), which contains stored float-

ing-point operate (FPop) instructions under execution and their addresses. The

execution unit controls the load unit, the store unit, and the datapath unit. The FPU

depends upon the IU to access all addresses and control signals for memory access.

Floating-point loads and stores are executed in conjunction with the IU, which provides

addresses and control signals while the FPU supplies or stores the data. Instruction

fetch for integer and floating-point instructions is provided by the IU.

The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR

is a 32-bit status and control register. It keeps track of rounding modes, floating-point

trap types, queue status, condition codes, and various IEEE exception information. The

floating-point queue contains the floating-point instruction currently under execution,

along with its corresponding address.

4204C–AERO–05/05

5962-0324601Q9A Related Products

	5962-0324601Q9A	5962-0324601VXC	5962-0324601V9A	5962-0324601QXC
Description	RISC Microprocessor, 32-Bit, 15MHz, CMOS, CQFP256, CERAMIC, QFP-256	RISC Microprocessor, 32-Bit, 15MHz, CMOS, CQFP256, CERAMIC, QFP-256	RISC Microprocessor, 32-Bit, 15MHz, CMOS, CQFP256, CERAMIC, QFP-256	RISC Microprocessor, 32-Bit, 15MHz, CMOS, CQFP256, CERAMIC, QFP-256
Parts packaging code	QFP	QFP	QFP	QFP
package instruction	QFF,	QFF,	QFF,	QFF,
Contacts	256	256	256	256
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
Address bus width	32	32	32	32
bit size	32	32	32	32
boundary scan	YES	YES	YES	YES
maximum clock frequency	30.3 MHz	30.3 MHz	30.3 MHz	30.3 MHz
External data bus width	32	32	32	32
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	NO	NO	NO	NO
JESD-30 code	S-CQFP-F256	S-CQFP-F256	S-CQFP-F256	S-CQFP-F256
length	37.085 mm	37.085 mm	37.085 mm	37.085 mm
low power mode	YES	YES	YES	YES
Number of terminals	256	256	256	256
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF	QFF	QFF	QFF
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Filter level	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class Q
Maximum seat height	3.18 mm	3.18 mm	3.18 mm	3.18 mm
speed	15 MHz	15 MHz	15 MHz	15 MHz
Maximum supply voltage	3.45 V	3.45 V	3.45 V	3.45 V
Minimum supply voltage	3.15 V	3.15 V	3.15 V	3.15 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	FLAT	FLAT	FLAT	FLAT
Terminal pitch	0.508 mm	0.508 mm	0.508 mm	0.508 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
width	37.085 mm	37.085 mm	37.085 mm	37.085 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Base Number Matches	1	1	1	1

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