Integrated Device Technology, Inc.
FAST CMOS 16-BIT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
IDT54/74FCT162511AT/CT
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
Typical tsk(o) (Output Skew) < 250ps, clocked mode
Low input and output leakage
≤1µA
(max)
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of –40°C to +85°C
V
CC
= 5V
±10%
Balanced Output Drivers:
±24mA
(commercial)
±16mA
(military)
Series current limiting resistors
Generate/Check, Check/Check modes
Open drain parity error allows wire-OR
DESCRIPTION:
The FCT162511AT/CT 16-bit registered/latched transceiver
with parity is built using advanced dual metal CMOS technol-
ogy. This high-speed, low-power transceiver combines D-
type latches and D-type flip-flops to allow data flow in transpar-
ent, latched or clocked modes. The device has a parity
generator/cheker in the A-to-B direction and a parity checker
in the B-to-A direction. Error checking is done at the byte level
with separate parity bits for each byte. Separate error flags
exits for each direction with a single error flag indicating an
error for either byte in the A-to-B direction and a second error
flag indicating an error for either byte in the B-to-A direction.
The parity error flags are open drain outputs which can be tied
together and/or tied with flags from other devices to form a
single error flag or interrupt. The parity error flags are enabled
by the
OExx
control pins allowing the designer to disable the
error flag during combinational transitions.
The control pins LEAB, CLKAB and
OEAB
control opera-
tion in the A-to-B direction while LEBA, CLKBA and
OEBA
control the B-to-A direction.
GEN
/CHK is only for the selection
of A-to-B operation, the B-to-A direction is always in checking
mode. The ODD/
EVEN
select is common between the two
directions. Except for the ODD/
EVEN
control, independent
operation can be achieved between the two directions by
using the corresponding control lines.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM:
LEAB
CLKAB
Data
16
Parity
GEN/CHK
Byte
Parity
Generator/
Checker
2
Latch/
Register
Parity, data
18
OEAB
B0-15
PB1,2
PERB
(Open Drain)
A0-15
PA1,2
ODD/EVEN
LEBA
CLKBA
Parity, data
18
OEBA
PERA
(Open Drain)
Latch/
Register
Byte
Parity
Checking
Parity, Data
18
2916 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC–2916/5
5.11
1
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
ODD/EVEN
OEAB
LEBA
CLKBA
CLKAB
LEAB
C
A
0
- A
7
D
C
D
OEBA
C
D
B
0
- B
7
C
D
P
O
C
D
C
D
P
C
D
C
D
PB
1
PA
1
I
C
A
8
- A
15
D
C
D
C
D
B
8
- B
15
C
D
P
O
C
D
C
D
C
D
C
D
C
D
C
PA
2
I
PB
2
C
GEN/CHK
D
PERB
(Open Drain)
C
D
P
2916 drw 02
PERA
(Open Drain)
D
5.11
2
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEAB
LEAB
PA
1
GND
A
0
A
1
V
CC
A
2
A
3
A
4
A
5
A
6
A
7
GND
PERA
A
8
A
9
A
10
A
11
A
12
A
13
V
CC
A
14
A
15
GND
PA
2
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
56
55
54
53
52
51
50
49
48
47
46
45
44
GEN/CHK
CLKAB
PB
1
GND
B
0
B
1
V
CC
B
2
B
3
B
4
B
5
B
6
B
7
PERB
GND
B
8
B
9
B
10
B
11
B
12
B
13
V
CC
B
14
B
15
GND
PB
2
CLKBA
ODD/EVEN
OEAB
LEAB
PA
1
GND
A
0
A
1
V
CC
A
2
A
3
A
4
A
5
A
6
A
7
GND
PERA
A
8
A
9
A
10
A
11
A
12
A
13
V
CC
A
14
A
15
GND
PA
2
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GEN/CHK
CLKAB
PB
1
GND
B
0
B
1
V
CC
B
2
B
3
B
4
B
5
B
6
B
7
PERB
GND
B
8
B
9
B
10
B
11
B
12
B
13
V
CC
B
14
B
15
GND
PB
2
CLKBA
ODD/EVEN
14 SO56-1 43
SO56-2
15 SO56-3 42
16
17
18
19
20
21
22
23
24
25
26
27
28
41
40
39
38
37
36
35
34
33
32
31
30
29
SSOP/
TSSOP/TVSOP
TOP VIEW
2916 drw 03
CERPACK
TOP VIEW
2916 drw 04
5.11
3
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
V
TERM(2)
Terminal Voltage with Respect to –0.5 to +7.0
GND
(3)
Terminal Voltage with Respect to
V
TERM
–0.5 to
GND
V
CC
+0.5
T
STG
Storage Temperature
–65 to +150
I
OUT
DC Output Current
–60 to +120
Unit
V
V
°C
mA
PIN DESCRIPTION
Pin Names
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
Parity Error (Open Drain) on A Outputs
Parity Error (Open Drain) on B Outputs
A-to-B Parity Input, B-to-A Parity Output
B-to-A Parity Input, A-to-B Parity Output
Parity Mode Selection Input
A to B Port Generate or Check Mode Input
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
2916 lnk 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. Open drain and all device terminals except FCT162XXXT Output and I/O
terminals.
3. Output and I/O terminals for FCT162XXXT.
PERA
PERB
PAx
(1)
PBx
ODD/
EVEN
GEN
/CHK
FUNCTION TABLE
(1,4)
OEAB
H
L
L
L
L
L
L
Inputs
LEAB
CLKAB
X
H
H
L
L
L
L
X
X
X
↑
↑
L
H
Ax
X
L
H
L
H
X
X
Outputs
Bx
Z
L
H
L
H
B
(2)
B
(3)
2916 tbl 03
NOTES:
1. The PAx pin input is internally disabled during parity generation. This
means that when generating parity in the A to B direction there is no need
to add a pull up resistor to guarantee state. The pin will still function
properly as the parity output for the B to A direction.
NOTES:
2916 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA
,
LEBA, and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
↑
= LOW-to-HIGH Transition
5.11
4
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
I/O
I/O
Capacitance
C
O
Open Drain
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
3.5
Max.
6.0
8.0
6.0
Unit
pF
pF
pF
2916 lnk 04
FUNCTION TABLE
(PARITY GENERATION)
(1, 2, 3, 4, 5)
A
0
- A
7
, Total Number
of inputs that are high
1, 3, 5 or 7
1, 3, 5 or 7
0, 2, 4, 6 or 8
0, 2, 4, 6 or 8
ODD/
EVEN
L
H
L
H
PB
1
H
L
L
H
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE
(PARITY CHECKING)
(1, 2, 3, 4)
A
0
- A
7
and PA
1 (5)
, Total Number
of inputs that are high
1, 3, 5, 7 or 9
1, 3, 5, 7 or 9
0, 2, 4, 6 or 8
0, 2, 4, 6 or 8
ODD/
EVEN
L
H
L
H
2916 tbl 06
NOTES:
1. Conditions shown are for
GEN
/CHK = L,
OEAB
= L,
OEBA
= H.
2. A-to-B parity checking is shown. B-to-A is capable of parity checking while
A-to-B is performing generation. B-to-A will not generate parity.
3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control
as an edge triggered clock.
4. Conditions shown are for the byte A
0
-A
7
. The byte A
8
-A
15
is similiar but
will output the parity on PB
2
.
5. The error flag
PERB
will remain in a high state during parity generation.
PERB
L
H
(6)
H
(6)
L
2916 tbl 05
NOTES:
1. Conditions shown are for
GEN
/CHK = H,
OEAB
= L,
OEBA
= H.
2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses
OEBA
= L,
OEAB
= H and errors will be indicated on
PERA
.
3. In parity checking mode the parity bits will be transmitted unchanged along
with the corresponding data regardless of parity errors. (PB
1
= PA
1
).
4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control
as an edge triggered clock.
5. Conditions shown are for the byte A
0
-A
7
and PA
1
. The byte A
8
-A
15
and
PA
2
is similiar.
6. The parity error flag
PERB
is a combined flag for both bytes A
0
-A
7
and A
8
-
A
15
. If a parity error occurs on either byte
PERB
will go low.
PERB
is an
open drain output which must be externally pulled up to achieve a logic
HIGH.
5.11
5
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