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-
© Nexperia B.V. (year). All rights reserved.
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PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Rev. 01 — 14 June 2002
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHP63NQ03LT in SOT78 (TO-220AB)
PHB63NQ03LT in SOT404 (D
2
-PAK)
PHD63NQ03LT in SOT428 (D-PAK).
1.2 Features
s
Logic level compatible
s
Low gate charge
1.3 Applications
s
DC to DC converters
s
Switched mode power supplies
1.4 Quick reference data
s
V
DS
= 30 V
s
P
tot
= 111 W
s
I
D
= 68.9 A
s
R
DSon
≤
13 mΩ
2. Pinning information
Table 1:
1
2
3
mb
Pinning - SOT78, SOT404, SOT428 simplified outline and symbol
Simplified outline
[1]
Pin Description
gate (g)
drain (d)
source (s)
mounting base,
connected to drain (d)
Symbol
mb
mb
mb
d
g
s
2
2
1
3
MBK116
MBB076
1
Top view
3
MBK091
MBK106
1 2 3
SOT78 (TO-220)
[1]
SOT404 (D
2
-PAK)
SOT428 (D-PAK)
It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.
Philips Semiconductors
PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
peak gate-source voltage
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
mb
= 25
°C
peak source (diode forward) current T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
t
p
≤
50
µs;
pulsed; duty cycle = 25 %
T
mb
= 25
°C;
V
GS
= 10 V;
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 10 V;
Figure 2
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
mb
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
≤
175
°C
25
°C ≤
T
j
≤
175
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
-
−55
−55
-
-
Max
30
30
±20
±25
68.9
48.7
240
111
+175
+175
68.9
48.7
Unit
V
V
V
V
A
A
A
W
°C
°C
A
A
Source-drain diode
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
2 of 14
Philips Semiconductors
PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
120
Pder
(%)
80
03aa16
120
Ider
(%)
80
03aa24
40
40
0
0
50
100
150
200
Tmb (°C)
0
0
50
100
150
200
Tmb (°C)
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
103
ID
(A)
03ai84
Limit RDSon = VDS / ID
tp = 10
µs
102
100
µs
10
DC
1 ms
1
1
10
VDS (V)
10
T
mb
= 25
°C;
I
DM
is single pulse; V
GS
= 10V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
3 of 14
Philips Semiconductors
PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
4. Thermal characteristics
Table 3:
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Conditions
Min Typ Max Unit
-
-
-
-
-
60
75
50
1.35 K/W
-
-
-
K/W
K/W
K/W
thermal resistance from junction to mounting base
Figure 4
thermal resistance from junction to ambient
SOT78
SOT428
SOT404 and SOT428
vertical in still air
SOT428 minimum footprint;
mounted on a PCB
SOT404 minimum footprint;
mounted on a PCB
Symbol Parameter
4.1 Transient thermal impedance
10
Zth(j-mb)
(K/W)
03ai83
1
δ
= 0.5
0.2
0.1
10-1
0.05
0.02
single pulse
10-2
10-5
tp
T
10-4
10-3
10-2
tp (s)
10-1
t
P
δ
=
tp
T
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
4 of 14