Integrated Device Technology, Inc.
BUS-MATCHING
BIDIRECTIONAL FIFO
512 x 18-BIT – 1024 x 9-BIT
1024 x 18-BIT – 2048 x 9-BIT
DESCRIPTION:
IDT72510
IDT72520
FEATURES:
• Two side-by-side FIFO memory arrays for bidirectional
data transfers
• 512 x 18-Bit – 1024 x 9-Bit (IDT72510)
• 1024 x 18-Bit – 2048 x 9-Bit (IDT72520)
• 18-bit data bus on Port A side and 9-bit data bus on Port
B side
• Can be configured for 18-to-9-bit, 36-to-9-bit, or 36-to-18-
bit communication
• Fast 25ns access time
• Fully programmable standard microprocessor interface
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Two programmable flags, Almost-Empty and Almost-Full
for each FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• Any of the eight internal flags can be assigned to four
external flag pins
• Flexible reread/rewrite capabilities.
• On-chip parity checking and generation
• Standard DMA control pins for data exchange with
peripherals
• IDT72510 and IDT72520 available in the the 52-pin PLCC
package
The IDT72510 and IDT72520 are highly integrated first-
in, first-out memories that enhance processor-to-processor
and processor-to-peripheral communications. IDT BiFIFOs
integrate two side-by-side memory arrays for data transfers
in two directions.
The BiFIFOs have two ports, A and B, that both have
standard microprocessor interfaces. All BiFIFO operations
are controlled from the 18-bit wide Port A. The BiFIFOs
incorporate bus matching logic to convert the 18-bit wide
memory data paths to the 9-bit wide Port B data bus. The
BiFIFOs have a bypass path that allows the device con-
nected to Port A to pass messages directly to the Port B
device.
Ten registers are accessible through Port A, a
Command Register, a Status Register, and eight Configuration
Registers.
The IDT BiFIFOs have programmable flags. Each FIFO
memory array has four internal flags, Empty, Almost-Empty,
Almost-Full and Full, for a total of eight internal flags. The
Almost-Empty and Almost-Full flag offsets can be set to any
depth through the Configuration Registers. These eight inter-
nal flags can be assigned to any of four external flag pins
(FLG
A
-FLG
D
) through one Configuration Register.
Port B has parity, reread/rewrite and DMA functions. Par-
ity generation and checking can be done by the BiFIFO on
data passing through Port B. The Reread and Rewrite con-
SIMPLIFIED BLOCK DIAGRAM
18-Bit
FIFO
18-bits
Data
Bypass Path
9-bits
9-bits
Data
Port
A
18-Bit
FIFO
Port
B
Registers
Control
Processor
Interface
A
Processor
Interface
B
Control
Flags
Programmable
Flag Logic
Handshake
Interface
DMA
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
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COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1995
DSC-2669/-
5.31
1
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
trols will read or write Port B data blocks multiple times. The
BiFIFOs have three pins, REQ, ACK and CLK, to control
DMA transfers from Port B devices.
PIN CONFIGURATION
LDREW
LDRER
GND
GND
D
A16
DS
A
V
CC
D
A9
D
A8
INDEX
7 6 5 4
D
A10
D
A11
D
A12
D
A13
D
A14
D
A15
D
A17
A
0
A
1
FLG
D
FLG
C
FLG
B
FLG
A
8
9
10
11
12
13
14
15
16
17
18
19
20
3 2
RS
1
52 51 50 49 48 47
46
45
44
43
42
41
D
A4
D
A3
D
A2
D
A1
D
A0
D
A7
D
A6
D
A5
J52-1
40
39
38
37
36
35
34
CS
A
R/
W
A
RER
REW
REQ
ACK
CLK
D
B0
21 22 23 24 25 26 27 28 29 30 31 32 33
W
B
(R/
W
B
)
R
B
(
DS
B
)
D
B8
D
B7
D
B6
D
B5
D
B4
D
B3
D
B2
GND
PLCC
TOP VIEW
GND
5.31
V
CC
D
B1
2
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
DA0-DA15
DA16-DA17
Name
Data A
Parity A
I/O
I/O
I/O
Description
Data inputs and outputs for 16 bits of the 18-bit Port A bus.
DA16 is the parity bit for DA0-DA7. DA17 is the parity bit for DA8-
DA15. DA16 and DA17 can be used as two extra data bits if the
parity generate function is disabled.
Port A is accessed when Chip Select A is LOW.
Data is written into Port A on the rising edge of Data Strobe when
Chip Select is LOW. Data is read out of Port A on the falling edge of
Data Strobe when Chip Select is LOW.
This pin controls the read or write direction of Port A. When
CS
A is
LOW and R/
W
A is HIGH, data is read from Port A on the falling edge
of
DS
A. When
CS
A is LOW and R/
W
A is LOW, data is written into
Port A on the rising edge of
DS
A.
When Chip Select A is asserted, A0, A1, and Read/Write A are used
to select one of six internal resources.
Data inputs and outputs for 8 bits of the 9-bit Port B bus.
DB8 is the parity bit for DB0-DB7. DB8 can be used as a data bit if
the parity generate function is disabled.
If Port B is programmed to processor mode, this pin functions as an
input. If Port B is programmed to peripheral mode this pin functions
as an output. This pin can function as part of an Intel-style interface
(
R
B) or as part of a Motorola-style interface (
DS
B). As an Intel-style
interface, data is read from Port B on a falling edge of
R
B. As a
Motorola-style interface, data is read on the falling edge of
DS
B or
written on the rising edge of
DS
B through Port B. The Default is Intel-
style processor mode (
R
B as an input).
If Port B is programmed to processor mode, this pin functions as an
input. If Port B is programmed to peripheral mode this pin functions
as an output. This pin can function as part of an Intel-style interface
(
W
B) or as part of a Motorola-style interface (R/
W
B). As an Intel
style interface, data is written to Port B on a rising edge of
W
B. As
a Motorola-style interface, data is read (R/
W
B = HIGH) or written (R/
W
B = LOW) to Port B in conjunction with a Data Strobe B falling or
rising edge. The Default is Intel-style processor mode (
W
B as input).
Loads A-to-B FIFO Read Pointer with the value of the Reread
Pointer when LOW.
Loads B-to-A FIFO Write Pointer with the value of the Rewrite
Pointer when LOW.
Loads the Reread Pointer with the value of the A-to-B FIFO Read
Pointer when HIGH. This signal is accessible through the Command
Register.
Loads the Rewrite Pointer with the value of the B-to-A FIFO Write
Pointer when HIGH. This signal is accessible through the Command
Register.
When Port B is programmed in peripheral mode, asserting this pin
begins a data transfer. Request can be programmed either active
HIGH or active LOW.
2669 tbl 01
CS
A
DS
A
R/
W
A
Chip Select A
Data Strobe A
I
I
Read/Write A
I
A0, A1
DB0-DB7
DB8
Addresses
Data B
Parity B
Read B
I
I/O
I/O
I or O
R
B (
DS
B)
W
B (R/
W
B)
Write B
I or O
RER
REW
LDRER
Reread
Rewrite
Load Reread
I
I
I
LDREW
Load Rewrite
I
REQ
Request
I
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3
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
ACK
Name
Acknowledge
I/O
O
Description
When Port B is programmed in peripheral mode, Acknowledge is
asserted in response to a Request signal. This confirms that a data
transfer may begin. Acknowledge can be programmed either active
HIGH or active LOW.
This pin is used to generate timing for ACK,
R
B,
W
B,
DS
B and R/
W
B when Port B is in the peripheral mode.
These four outputs pins can be assigned to any one of the eight
internal flags in the BiFIFO. Each of the two internal FIFOs (A-to-B
and B-to-A) has four internal flags: Empty, Almost-Empty, Almost-
Full, and Full. If parity checking is enabled, the FLGA pin can also
be assigned as a parity error output.
A LOW on this pin will perform a reset of all BiFIFO functions.
Software reset can be achieved through command register.
There are two +5V power pins on all four devices.
There are four ground pins
2669 tbl 02
CLK
FLGA-FLGD
Clock
Flags
I
O
RS
VCC
GND
Reset
Power
Ground
I
5.31
4
ReRead Pointer
Reread
Read Pointer
Port B
Control
(D
B8
)
MUX
Load Reread
LDRER †
LDREW †
Write Pointer
CS
A
DS
A
R/
W
A
A→B FIFO
Parity Bit 17
Parity Bit 16
Port A
Control
A
1
A
0
1
RER
REW
R
B
(
DS
B
) ††
W
B
(R/
W
B
) ††
Data Bits 8-15
Parity
Generate/
Check
18
8
Read Parity Error
(D
B0-
DB
7
)
8
8
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
Data Bits 0-7
Bypass Path
DETAILED BLOCK DIAGRAM
Port A
D
A0
-
D
A17
MUX
Port B
D
B0
-
D
B8
Parity
Generate/
Check
9
(D
A0
-D
A7
,D
A16
)
Parity Bit 17
Parity Bit 16
9
Odd Byte
Register
B→A FIFO
Data Bits 8-15
Data Bits 0-7
8
5.31
18
Reset
RS
†
DMA
Control
REQ*
ACK*
CLK
Read Pointer
Rewrite
ReWrite Pointer
Write Pointer
Write
Parity Error
Load Rewrite
Command
16
(D
A0
-D
A15
)
Status
Configuration 0
FLG
A*
FLG
B*
FLG
C*
FLG
D*
Programmable
Flag Logic
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
Configuration 7
COMMERCIAL TEMPERATURE RANGE
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5
NOTES:
(*) Can be programmed either active high or active low in internal configuration registers.
(†) Accessible through internal registers.
(††) Can be programmed through an internal configuration register to be either an input or an output.
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