128K x 36, 256K x 18,
3.3V Synchronous ZBT™ SRAMs
3.3V I/O, Burst Counter,
Flow-Through Outputs
x
x
IDT71V3557S
IDT71V3559S
IDT71V3557SA
IDT71V3559SA
Features
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates
the need to control
OE
Single R/W (READ/WRITE) control pin
W
4-word burst capability (Interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
BW
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V (±5%) I/O Supply (V
DDQ
)
Optional Boundary Scan JTAG Interface (IEEE 1149.1
complaint)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array (fBGA)
x
x
x
x
x
x
x
x
x
Description
The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are
designed to eliminate dead bus cycles when turning the bus around
between reads and writes, or writes and reads. Thus they have been
given the name ZBT
TM
, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle the associated data cycle occurs, be
it read or write.
The IDT71V3557/59 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3557/59
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three is not asserted
when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will
be completed. The data bus will tri-state one cycle after chip is de-
selected or a write is initiated.
The IDT71V3557/59 have an on-chip burst counter. In the burst
mode, the IDT71V3557/59 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO
input pin. The
LBO
pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V3557/59 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
Synchronous
Static
Static
5282 tbl 01
Pin Description Summary
A
0
-A
17
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
CE
1
, CE
2
,
CE
2
OE
R/
W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/
LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
1
©2004 Integrated Device Technology, Inc.
OCTOBER 2004
DSC-5282/07
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
-A
17
ADV/
LD
Pin Function
Address Inputs
Advance / Load
I/O
I
I
Active
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/
LD
low,
CEN
low, and true chip enables.
ADV/
LD
is a synchronous input that is used to load the internal registers with new address and control when it
is sampled low at the rising edge of clock with the chip selected. When ADV/
LD
is low with the chip
deselected, any burst in progress is terminated. When ADV/
LD
is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/
LD
is
sampled high.
R/
W
signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place one clock cycle later.
Sy nchronous Clock Enable Input. When
CEN
is sampled high, all other synchronous inputs, including clock
are ignored and outputs remain unchanged. The effect of
CEN
sampled high on the device outputs is as if
the low to high clock transition did not occur. For normal operation,
CEN
must be samp led low at rising edge
of clock.
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write
cycles (When R/
W
and ADV/
LD
are sampled low) the appropriate byte write signal (
BW
1
-
BW
4
) must be valid.
The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when
R/
W
is sampled high. The ap propriate byte(s) of data are written into the device one cycle later.
BW
1
-
BW
4
can all be tied low if always doing write to the entire 36-bit word.
Synchronous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to enable the IDT71V3557/59. (
CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/
LD
low at the rising edge of clock, initiates a deselect
cycle. The ZBT
TM
has a one cycle dese lect, i.e., the data bus will tri-state one clock cycle after deselect is
initiated.
Synchronous active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable the chip. CE
2
has inverted
polarity but otherwise identical to
CE
1
and
CE
2
.
This is the clock input to the IDT71V3557/59. Except for
OE
, all timing references for the device are made
with respect to the rising edge of CLK.
Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data
output path is flow-through (no output register).
Burst order selection input. When
LBO
is high the Interleaved burst sequence is selected. When
LBO
is low
the Linear burst sequence is selected.
LBO
is a static input, and it must not change during device operation..
Asynchronous output enable.
OE
must be low to read data from the 71V3557/59. When
OE
is HIGH the I/O
pins are in a high-impedance state.
OE
does not need to be actively controlled for read and write cycles. In
normal operation,
OE
can be tied low.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also rese ts using TMS and TCK per IEEE 1149.1. If not used
TRST
can
be left floating. This pin has an internal pullup.
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3557/3559 to
its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
3.3V core power supply.
3.3V I/O Supply.
Ground.
5282 tbl 02
R/
W
Read / Write
Clock Enable
I
I
N/A
LOW
CEN
BW
1
-
BW
4
Individual Byte
Write Enables
I
LOW
CE
1
,
CE
2
Chip Enables
I
LOW
CE
2
CLK
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Chip Enable
Clock
Data Input/Output
Linear Burst Order
Output Enable
I
I
I/O
I
I
HIGH
N/A
N/A
LOW
LOW
LBO
OE
TMS
TDI
TCK
TDO
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset
(Optional)
I
I
I
O
N/A
N/A
N/A
N/A
TRST
I
LOW
ZZ
V
DD
V
DDQ
V
SS
Sleep Mode
Power Supply
Power Supply
Ground
I
N/A
N/A
N/A
HIGH
N/A
N/A
N/A
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram 128K x 36
LBO
Address A [0:16]
CE
1
, CE
2
CE
2
R/W
CEN
ADV/LD
BWx
Input Register
DI
DO
D
Q
Control
D
Q
128K x 36 BIT
MEMORY ARRAY
Address
D
Clk
Q
Control Logic
Mux
Clock
Sel
OE
Gate
TMS
TDI
TCK
TRST
(optional)
Data I/O [0:31], I/O P[1:4]
JTAG
(SA Version)
,
TDO
5282 drw 01
6.42
3
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram 256K x 18
LBO
Address A [0:17]
CE
1
, CE
2
CE
2
R/W
CEN
ADV/LD
BWx
D
Clk
D
Q
Control
D
Q
256K x 18 BIT
MEMORY ARRAY
Address
Input Register
DI
DO
Q
Control Logic
Mux
Clock
Sel
OE
Gate
TMS
TDI
TCK
TRST
(optional)
Data I/O [0:15], I/O P[1:2]
JTAG
(SA Version)
,
TDO
5282 drw 01a
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.135
3.135
0
2.0
2.0
-0.3
(1)
Typ.
3.3
3.3
0
____
____
____
Max.
3.465
3.465
0
V
DD
+ 0.3
V
DDQ
+ 0.3
(2)
0.8
Unit
V
V
V
V
V
V
5282 tbl 04
NOTES:
1. V
IL
(min.) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
2. V
IH
(max.) = +6.0V for pulse width less than t
CYC
/2, once per cycle.
6.42
4
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
(1)
0°C to +70°C
-40°C to +85°C
V
SS
0V
0V
V
DD
3.3V±5%
3.3V±5%
V
DDQ
3.3V±5%
3.3V±5%
5282 tbl 05
NOTES:
1. T
A
is the "instant on" case temperature.
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
P3
I/O
16
I/O
17
V
DDQ
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DDQ
I/O
22
I/O
23
V
SS
(1)
V
DD
V
DD
(2)
V
SS
I/O
24
I/O
25
V
DDQ
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DDQ
I/O
30
I/O
31
I/O
P4
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/
LD
NC
(3)
NC
(3)
A
8
A
9
Pin Configuration 128K x 36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
P2
I/O
15
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
SS
(1)
V
DD
V
SS/ZZ
(1,4)
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
5282 drw 02
,
NOTES:
1. Pins 14, 64, and 66 do not have to be connected directly to V
SS
as long as the input voltage is < V
IL
.
2. Pin 16 does not have to be connected directly to V
DD
as long as the input voltage is > V
IH
.
3. Pins 83 and 84 are reserved for future 8M and 16M respectively.
4. Pin 64 supports ZZ (sleep mode) for the latest die revisions.
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Top View
100 TQFP
6.42
5
京公网安备 11010802033920号
EEWORLD
