LOW POWER 2V CMOS SRAM
1 MEG (128K x 8-BIT)
Integrated Device Technology, Inc.
ADVANCE
INFORMATION
IDT71T024
FEATURES:
•
•
•
•
•
•
•
128K x 8 Organization
Wide Operating Voltage Range: 1.8V to 2.7V
Speed Grades: 150ns, 200ns
Low Operating Power: 11mA (max)
Low Standby Power: 5µA (max)
Low-Voltage Data Retention: 1.5V (min)
Available in 32-pin, 13.4mm x 8mm Type I TSOP pack-
age
DESCRIPTION:
The IDT71T024 is a 1,048,576-bit very low-power Static
RAM organized as 128K x 8. It is fabricated using IDT’s high-
reliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides
a cost-effective solution for low-power memory needs. It uses
a 6-transistor memory cell.
Operation is from a single extended-range 2.5V supply.
This extended supply range makes the device ideally suited
for unregulated battery-powered applications. Fully static
asynchronous circuitry is used, requiring no clocks or refresh
for operation.
The IDT71T024 is packaged in a JEDEC standard 32-pin
TSOP Type I.
FUNCTIONAL BLOCK DIAGRAM
A
0
•
•
•
A
16
ADDRESS
DECODER
•
•
•
1,048,576-BIT
MEMORY ARRAY
I/O
0
– I/O
7
•
8
8
I/O CONTROL
8
WE
OE
CS1
CS2
CONTROL
LOGIC
3779 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
©1997
Integrated Device Technology, Inc.
MAY 1997
DSC-3779/1
1
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A
11
A
9
A
8
A
13
WE
CS2
A
15
V
DD
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP (I)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CS1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
V
SS
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
3779 drw 02
TSOP
TOP VIEW
TRUTH TABLE
(1)
CS1
H
X
L
L
L
CS2
X
L
H
H
H
PIN DESCRIPTIONS
WE
X
X
H
L
H
I/O
0
-I/O
7
High-Z
High-Z
DATA
OUT
DATA
IN
High-Z
Function
Deselected - Standby
Deselected - Standby
Read
Write
Outputs Disabled
3779 tbl 02
OE
X
X
L
X
H
A
0
– A
16
Address Inputs
Chip Select
Chip Select
Write Enable
Output Enable
Data Input/Output
Power
Ground
Input
Input
Input
Input
Input
I/O
Pwr
Gnd
3779 tbl 01
CS1
CS2
WE
OE
I/O
0
- I/O
7
V
DD
V
SS
NOTE:
1.H = V
IH
, L = V
IL
, X = Don't care.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 1dV
V
OUT
= 1dV
Max.
6
7
Unit
pF
pF
NOTE:
3779 tbl 06
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
2
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with
Respect to V
SS
Terminal Voltage with
Respect to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com’l. and Ind'l.
–0.5 to +3.6
–0.5 to V
DD
+0.5V
–55 to +125
–55 to +125
1.0
20
Unit
V
V
°C
°C
W
mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
V
SS
0V
0V
V
DD
1.8V to 2.7V
1.8V to 2.7V
3779 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
1.8
0
V
DD
x 0.7
–0.3
(2)
Max.
2.7
0
V
DD
+ 0.3
(1)
V
DD
x 0.3
Unit
V
V
V
V
NOTES:
3779 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. Input, Output,and I/O terminals; 3.6V maximum.
NOTE:
3779 tbl 05
1. V
IH
(max.) = V
DD
+ 1.5V for pulse width less than 5ns, once per cycle.
2. V
IL
(min.) = –1.5V for pulse width less than 5ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
V
DD
= 1.8V to 2.7V, Commercial and Industrial Temperature Ranges
Symbol
|I
LI
|
|I
LO
|
V
OH
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Test Conditions
V
DD
= Max., V
IN
= V
SS
to V
DD
V
DD
= Max.,
CS
= V
IH
, V
OUT
= V
SS
to V
DD
V
DD
= 1.8 to 2.7V
V
DD
= 2.3 to 2.7V
V
DD
= 1.8 to 2.7V
V
DD
= 2.3 to 2.7V
I
OH
= –0.3mA
I
OH
= –2mA
I
OL
= 0.3mA
I
OL
= 2mA
Min.
—
—
V
DD
- 0.2
1.7
—
—
Max.
1
1
—
—
0.2
0.4
3779 tbl 07
Unit
µA
µA
V
V
DC ELECTRICAL CHARACTERISTICS
(1, 2)
V
DD
= 1.8 to 2.7V, V
LC
= 0.2V, V
HC
= V
DD
–0.2V, Commercial and Industrial Temperature Ranges
Symbol
I
CC2
Parameter
Dynamic Operating Current
Test Conditions
Typ.
(5)
-70 ns
-100 ns
—
—
—
-40 to 85°C
0 to 70°C
40°C
25°C
NOTES:
1. All values are maximum guaranteed values.
2. Input low and high voltage levels are 0.2V and V
DD
-0.2V respectively for all tests.
3. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
).
4. f = 0 means no address input lines are changing .
5. Typical conditions are V
DD
= 2.0V and specified temperature.
Max.
11
9
4
10
5
2
1
Unit
mA
CS1
= V
LC
, CS2 = V
HC
, Outputs Open,
V
DD
= 2.7V, f = f
MAX
(3)
I
CC
I
SB1
Static Operating Current
Standby Supply Current
CS1
= V
LC
, CS2 = V
HC
, Outputs Open,
WE
= V
HC
, V
DD
= 2.7V, f = 0
(4)
CS1
and CS2 = V
HC
, or CS2 = V
LC
,
Outputs Open, V
DD
= 2.7V
mA
µA
—
—
—
—
3778 tbl 08
3
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(V
LC
= 0.2V, V
HC
= V
DD
- 0.2V)
Symbol
V
DR
I
CCDR
t
CDR
t
R(3)
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Test Condition
—
1)
CS1
≥
V
HC
and CS2
≥
V
HC
or
2) CS2
≤
VLC
Min.
1.5
—
0
t
RC(2)
Typ.
(1)
—
<1
—
—
Max.
—
5
—
—
Unit
V
µA
ns
ns
3779 tbl 09
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
LOW V
DD
DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
V
DD
t
CDR
1.8V
V
DR
≥
1.5V
V
IH
V
IH
3779 drw 05
1.8V
t
R
CS
V
DR
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to V
DD
3ns
V
DD
x 0.5
V
DD
x 0.5
See Figure 1
3779 tbl 10
AC TEST LOAD
V
DD
3070Ω
DATA
OUT
50pF*
3150Ω
3779 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
4
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
DD
= 1.8 to 2.7V, All Temperature Ranges)
71T024L150
Symbol
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ(1)
t
CHZ(1)
t
OE
t
OLZ(1)
t
OHZ(1)
t
OH
Write Cycle
t
WC
t
AW
t
CW
t
AS
t
WR
t
WP
t
DW
t
DH
t
OW(1)
t
WHZ(1)
Write Cycle Time
Address Valid to End of Write
Chip Select Low to End of Write
Address Set-up Time
Address Hold from End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
150
120
120
0
0
100
60
0
5
—
—
—
—
—
—
—
—
—
—
40
200
160
160
0
0
140
80
0
5
—
—
—
—
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3779 tbl 11
71T024L200
Min.
200
—
—
20
—
—
20
—
15
Max.
—
200
200
—
40
100
—
40
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
Min.
150
—
—
20
—
—
20
—
15
Max.
—
150
150
—
30
75
—
30
—
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
5
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