FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
Integrated Device Technology, Inc.
IDT54/74FCT16500AT/CT/ET
IDT54/74FCT162500AT/CT/ET
bit registered transceivers are built using advanced dual metal
CMOS technology. These high-speed, low-power 18-bit reg-
• Common features:
istered bus transceivers combine D-type latches and D-type
– 0.5 MICRON CMOS Technology
flip-flops to allow data flow in transparent, latched and clocked
– High-speed, low-power CMOS replacement for
modes. Data flow in each direction is controlled by output-
ABT functions
enable (OEAB and
OEBA
), latch enable (LEAB and LEBA)
–
Typical t
SK
(o) (Output Skew) < 250ps
and clock (
CLKAB
and
CLKBA
) inputs. For A-to-B data flow,
– Low input and output leakage
≤1µA
(max.)
the device operates in transparent mode when LEAB is HIGH.
– ESD > 2000V per MIL-STD-883, Method 3015;
When LEAB is LOW, the A data is latched if
CLKAB
is held at
> 200V using machine model (C = 200pF, R = 0)
a HIGH or LOW logic level. If LEAB is LOW, the A bus data is
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack stored in the latch/flip-flop on the HIGH-to-LOW transition of
CLKAB
. OEAB performs the output enable function on the B
– Extended commercial range of -40°C to +85°C
port. Data flow from B port to A port is similar but uses
OEBA
,
– V
CC
= 5V
±10%
LEBA and
CLKBA
. Flow-through organization of signal pins
• Features for FCT16500AT/CT/ET:
simplifies layout. All inputs are designed with hysteresis for
– High drive outputs (-32mA I
OH
, 64mA I
OL
)
improved noise margin.
– Power off disable outputs permit “live insertion”
The FCT16500AT/CT/ET are ideally suited for driving
– Typical V
OLP
(Output Ground Bounce) < 1.0V at
high-capacitance loads and low-impedance backplanes. The
V
CC
= 5V, T
A
= 25°C
output buffers are designed with power off disable capability
• Features for FCT162500AT/CT/ET:
to allow "live insertion" of boards when used as backplane
– Balanced Output Drivers:
±24mA
(commercial),
drivers.
±16mA
(military)
The FCT162500AT/CT/ET have balanced output drive
– Reduced system switching noise
with current limiting resistors. This offers low ground bounce,
– Typical V
OLP
(Output Ground Bounce) < 0.6V at
minimal undershoot, and controlled output fall times–reducing
V
CC
= 5V,T
A
= 25°C
the need for external series terminating resistors. The
FCT162500AT/CT/ET are plug-in replacements for the
DESCRIPTION:
FCT16500AT/CT/ET and ABT16500 for on-board bus inter-
The FCT16500AT/CT/ET and FCT162500AT/CT/ET 18- face applications.
FEATURES:
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
A
1
D
C
B
1
D
C
D
C
D
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
2548 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-2548/7
5.9
1
IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
SO56-1 43
SO56-2
SO56-3 42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
CLKBA
GND
2548 drw 02
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2548 drw 03
GND
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
CLKBA
GND
SSOP/
TSSOP/TVSOP
TOP VIEW
CERPACK
TOP VIEW
5.9
2
IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
OEAB
Description
A-to-B Output Enable Input
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input (Active LOW)
B-to-A Clock Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
2548 tbl 01
FUNCTION TABLE
(1,4)
Inputs
LEAB
CLKAB
X
H
H
L
L
L
L
X
X
X
↓
↓
H
L
Outputs
Bx
Z
L
H
L
H
B
(2)
B
(3)
OEBA
LEAB
LEBA
OEAB
L
H
H
H
H
H
H
Ax
X
L
H
L
H
X
X
CLKAB
CLKBA
Ax
Bx
NOTES:
2548 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA
,
LEBA, and
CLKBA
.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that
CLKAB
was LOW before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↓ =
HIGH-to-LOW Transition
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
V
TERM(2)
Terminal Voltage with Respect to –0.5 to +7.0
GND
–0.5 to
V
TERM(3)
Terminal Voltage with Respect to
GND
V
CC
+0.5
T
STG
Storage Temperature
–65 to +150
I
OUT
DC Output Current
–60 to +120
Unit
V
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
I/O
I/O
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max. Unit
6.0
pF
8.0
pF
2548 lnk 04
°
C
mA
NOTE:
1. This parameter is measured at characterization but not tested.
2548 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.9
3
IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= –40°C to +85°C, V
CC
= 5.0V
±
10%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= GND
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
Min.
2.0
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–
0.7
–
140
Max.
—
Unit
V
V
µA
0.8
±1
±1
±1
±1
±1
±1
–
1.2
–
225
—
µA
V
mA
mV
µA
100
5
V
CC
= Max., V
IN
= GND or V
CC
500
2548 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16500T
Symbol
I
O
V
OH
Parameter
Output Drive Current
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Max., V
O
= 2.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –3mA
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
I
OH
= –24mA MIL.
I
OH
= –32mA COM'L.
(4)
I
OL
= 48mA MIL.
I
OL
= 64mA COM'L.
≤
4.5V
Min.
–50
2.5
2.4
2.0
—
—
Typ.
(2)
—
Max.
–
180
—
—
—
0.55
±1
Unit
mA
V
V
V
V
µA
2548 lnk 06
3.5
3.5
3.0
0.2
—
V
OL
I
OFF
Output LOW Voltage
Input/Output Power Off Leakage
(5)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
OUTPUT DRIVE CHARACTERISTICS FOR FCT162500T
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –16mA MIL.
I
OH
= –24mA COM'L.
I
OL
= 16mA MIL.
I
OL
= 24mA COM'L.
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
2548 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is
±
5µA at T
A
= –55°C.
5.9
4
IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
V
IN
= V
CC
OEAB =
OEBA
= V
CC
or GND V
IN
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (
CLKAB
)
50% Duty Cycle
OEAB =
OEBA
= V
CC
LEAB = GND
One Bit Toggling
f
i
= 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (
CLKAB
)
50% Duty Cycle
OEAB =
OEBA
= V
CC
LEAB = GND
Eighteen Bits Toggling
f
i
= 2.5MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
0.5
75
Max.
1.5
120
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
—
0.8
1.7
mA
V
IN
= 3.4V
V
IN
= GND
—
1.3
3.2
V
IN
= V
CC
V
IN
= GND
—
3.8
6.5
(5)
V
IN
= 3.4V
V
IN
= GND
—
8.5
20.8
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
2548 tbl 08
5.9
5
DSP and ARM Processors
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